JPWO2016067161A1 - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

Provided is a transistor having stable electrical characteristics. Alternatively, a transistor having normally-off electrical characteristics is provided. An oxide semiconductor layer having crystallinity is formed over a substrate, oxygen is added to the oxide semiconductor layer by an ion implantation method while the substrate is heated, and an oxide semiconductor layer in which crystallinity hardly changes before and after the addition of oxygen is formed. A semiconductor element having the same is formed. In addition, oxygen or fluorine is added to the insulating layer in contact with the oxide semiconductor layer while the substrate is heated by an ion implantation method, so that the withstand voltage of the transistor is improved.

Description

The present invention relates to a transistor and a semiconductor device, for example. Alternatively, the present invention relates to a method for manufacturing a transistor and a semiconductor device, for example. Alternatively, the present invention relates to, for example, a display device, a light-emitting device, a lighting device, a power storage device, a storage device, a processor, and an electronic device. Alternatively, the present invention relates to a method for manufacturing a display device, a liquid crystal display device, a light-emitting device, a memory device, or an electronic device. Alternatively, the present invention relates to a display device, a liquid crystal display device, a light-emitting device, a memory device, and a driving method of an electronic device.

Note that one embodiment of the present invention is not limited to the above technical field. The technical field of one embodiment of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, a manufacture, or a composition (composition of matter).

Note that in this specification and the like, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. A display device, a light-emitting device, a lighting device, an electro-optical device, a semiconductor circuit, and an electronic device may include a semiconductor device.

A technique for forming a transistor using a semiconductor over a substrate having an insulating surface has attracted attention. The transistor is widely applied to semiconductor devices such as integrated circuits and display devices. Silicon is known as a semiconductor applicable to a transistor.

As silicon used for a semiconductor of a transistor, amorphous silicon and polycrystalline silicon are selectively used depending on the application. For example, when applied to a transistor included in a large display device, it is preferable to use amorphous silicon in which a technique for forming a film over a large-area substrate is established. On the other hand, when applied to a transistor included in a high-function display device in which a driver circuit is integrally formed, it is preferable to use polycrystalline silicon capable of manufacturing a transistor having high field-effect mobility. A method of forming polycrystalline silicon by performing heat treatment at high temperature or laser light treatment on amorphous silicon is known.

In recent years, development of transistors using oxide semiconductors (typically including In, Ga, and Zn) has become active. An oxide semiconductor has a long history, and in 1988, it has been disclosed to use a crystalline In—Ga—Zn oxide for a semiconductor element (see Patent Document 1). In 1995, a transistor using an oxide semiconductor was invented, and its electrical characteristics were disclosed (see Patent Document 2).

A transistor using an oxide semiconductor has different characteristics from a transistor using amorphous silicon and a transistor using polycrystalline silicon. For example, a display device using a transistor including an oxide semiconductor is known to have low power consumption. An oxide semiconductor can be formed by a sputtering method or the like, and thus can be used for a transistor included in a large display device. In addition, since a transistor including an oxide semiconductor has high field-effect mobility, a high-function display device in which a driver circuit is formed can be realized. Further, since it is possible to improve and use a part of the production facility for transistors using amorphous silicon, there is an advantage that capital investment can be suppressed.

JP-A-63-239117 11-505377

Another object is to provide a transistor having stable electrical characteristics. Another object is to provide a transistor having normally-off electrical characteristics. Another object is to provide a transistor with a small subthreshold swing value. Another object is to provide a transistor with a short channel effect. Another object is to provide a transistor with low leakage current during non-conduction. Another object is to provide a transistor with excellent electrical characteristics. Another object is to provide a highly reliable transistor. Another object is to provide a transistor having high frequency characteristics.

Another object is to provide a semiconductor device including the transistor. Another object is to provide a module including the semiconductor device. Another object is to provide an electronic device including the semiconductor device or the module. Another object is to provide a novel semiconductor device. Another object is to provide a new module. Another object is to provide a novel electronic device.

Note that the description of these problems does not disturb the existence of other problems. Note that one embodiment of the present invention does not have to solve all of these problems. Issues other than these will be apparent from the description of the specification, drawings, claims, etc., and other issues can be extracted from the descriptions of the specification, drawings, claims, etc. It is.

In one embodiment of the present invention, an oxide semiconductor layer having crystallinity is formed over a substrate, and oxygen is added to the oxide semiconductor layer while the substrate is heated, so that a semiconductor element including the oxide semiconductor layer is formed. Maintaining crystallinity even when oxygen is added by an ion implantation method to an oxide semiconductor layer having crystallinity over a substrate heated at 60 ° C to 500 ° C, preferably 250 ° C to 450 ° C. Can do.

In the structure of the above manufacturing method, oxygen is added by an ion implantation method or plasma treatment.

In the structure of the above manufacturing method, a dense oxide semiconductor layer can be obtained by performing heat treatment after adding oxygen to the oxide semiconductor. For the heat treatment, an RTA (Rapid Thermal Annealing) apparatus using lamp heating can also be used. The heat treatment by the RTA apparatus is effective for improving productivity because it takes a shorter time than a furnace. In this manner, by increasing the temperature and time of heat treatment, the oxide semiconductor layer can have a higher density and can be made closer to the physical properties of a single crystal.

In addition, oxygen is not added to the oxide semiconductor layer over the heated substrate, and oxygen is supplied to the insulating layer in contact with the oxide semiconductor layer over the heated substrate or the oxide semiconductor layer over the heated substrate. Oxygen may be added to the insulating layer.

Moreover, it is not limited to oxygen, You may add a fluorine to an insulating layer, heating a board | substrate. When fluorine is added to the insulating layer, the breakdown voltage of the semiconductor device is improved.

According to one embodiment of the present invention, a conductor is formed over a substrate, a first insulator is formed over the conductor, and a semiconductor having crystallinity is formed over the conductor through the first insulator. The second insulator is formed on the semiconductor, the third insulator is formed on the second insulator, and the second insulator is passed through the third insulator while the substrate is heated. This is a method for manufacturing a semiconductor device in which fluorine is added.

In the above structure, the second insulator is an insulator including oxygen and silicon.

In the above structure, the third insulator is an insulator including nitrogen and silicon.

In the structure of the above manufacturing method, fluorine is added by an ion implantation method or plasma treatment.

According to one embodiment of the present invention, a crystalline oxide semiconductor layer is formed over a substrate, a semiconductor element including the oxide semiconductor layer is formed, a barrier layer is formed over the semiconductor element, and the substrate is heated while the substrate is heated. This is a method for manufacturing a semiconductor device in which fluorine is added to a barrier layer.

In the above structure, the barrier layer is an insulator containing oxygen and aluminum.

In each of the above structures, the oxide semiconductor layer includes indium, an element M (Ti, Ga, Y, Zr, La, Ce, Nd, Sn, or Hf), zinc, and oxygen.

A transistor having stable electrical characteristics can be provided. Alternatively, a transistor having normally-off electrical characteristics can be provided. Alternatively, a transistor with a small subthreshold swing value can be provided. Alternatively, a transistor with a short channel effect can be provided. Alternatively, a transistor with low leakage current when not conducting can be provided. Alternatively, a transistor with excellent electrical characteristics can be provided. Alternatively, a highly reliable transistor can be provided. Alternatively, a transistor having high frequency characteristics can be provided.

Alternatively, a semiconductor device including the transistor can be provided. Alternatively, a module including the semiconductor device can be provided. Alternatively, an electronic device including the semiconductor device or the module can be provided. Alternatively, a novel semiconductor device can be provided. Alternatively, a new module can be provided. Alternatively, a novel electronic device can be provided.

Note that the description of these effects does not disturb the existence of other effects. Note that one embodiment of the present invention need not have all of these effects. It should be noted that the effects other than these are naturally obvious from the description of the specification, drawings, claims, etc., and it is possible to extract the other effects from the descriptions of the specification, drawings, claims, etc. It is.

It is process sectional drawing which shows 1 aspect of this invention. 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. 6 is a cross-sectional view illustrating a transistor according to one embodiment of the present invention. 6 is a cross-sectional view illustrating a transistor according to one embodiment of the present invention. FIG. 6 is a band diagram according to one embodiment of the present invention. 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. 6 is a cross-sectional view illustrating a transistor according to one embodiment of the present invention. 6 is a cross-sectional view illustrating a transistor according to one embodiment of the present invention. FIG. 10 is a circuit diagram illustrating a semiconductor device according to one embodiment of the present invention. FIG. 6 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. FIG. 6 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. FIG. 6 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. FIG. 10 is a circuit diagram illustrating a memory device according to one embodiment of the present invention. FIG. 6 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. FIG. 6 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. FIG. 6 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. FIG. 6 is a top view illustrating a semiconductor device according to one embodiment of the present invention. 1 is a block diagram illustrating a semiconductor device according to one embodiment of the present invention. FIG. 6 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. FIG. 6 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. 4A and 4B are a perspective view and a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. 1 is a block diagram illustrating a semiconductor device according to one embodiment of the present invention. FIG. 10 is a circuit diagram illustrating a semiconductor device according to one embodiment of the present invention. 4A and 4B are a circuit diagram, a top view, and a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. 6A and 6B are a circuit diagram and a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. FIG. 11 is a perspective view illustrating an electronic device according to one embodiment of the present invention. FIG. 6 is a Cs-corrected high-resolution TEM image in a cross section of a CAAC-OS and a schematic cross-sectional view of the CAAC-OS. The Cs correction | amendment high-resolution TEM image in the plane of CAAC-OS. 6A and 6B illustrate structural analysis by XRD of a CAAC-OS and a single crystal oxide semiconductor. The figure which shows the electron diffraction pattern of CAAC-OS. FIG. 6 shows changes in crystal parts of an In—Ga—Zn oxide due to electron irradiation. FIG. 6 is a schematic diagram illustrating a film formation model of CAAC-OS and nc-OS. 4A and 4B illustrate an InGaZnO ₄ crystal and a pellet. FIG. 6 is a schematic diagram illustrating a CAAC-OS film formation model. The figure explaining heat processing. The graph which shows an XRD spectrum using out-of-plane measurement. The figure which shows a cross-sectional TEM image. The figure which shows a cross-sectional TEM image. FIG. 6 illustrates a bonding state of silicon oxide.

Embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be easily understood by those skilled in the art that modes and details can be variously changed. In addition, the present invention is not construed as being limited to the description of the embodiments below. Note that in describing the structure of the present invention with reference to drawings, the same portions are denoted by the same reference numerals in different drawings. In addition, when referring to the same thing, a hatch pattern is made the same and there is a case where it does not attach | subject a code | symbol in particular.

Note that the size, the thickness of films (layers), or regions in drawings is sometimes exaggerated for simplicity.

Note that in this specification, the expression “film” and the expression “layer” can be interchanged with each other.

In many cases, the voltage indicates a potential difference between a certain potential and a reference potential (for example, a ground potential (GND) or a source potential). Thus, a voltage can be rephrased as a potential. Generally, the potential (voltage) is relative and is determined by a relative magnitude from a reference potential. Therefore, even when “ground potential” is described, the potential is not always 0V. For example, the lowest potential in the circuit may be the “ground potential”. Alternatively, an intermediate potential in the circuit may be a “ground potential”. In that case, a positive potential and a negative potential are defined based on the potential.

The ordinal numbers attached as the first and second are used for convenience and do not indicate the order of steps or the order of lamination. Therefore, for example, the description can be made by appropriately replacing “first” with “second” or “third”. In addition, the ordinal numbers described in this specification and the like may not match the ordinal numbers used to specify one embodiment of the present invention.

Note that even when “semiconductor” is described, for example, when the conductivity is sufficiently low, the semiconductor device may have characteristics as an “insulator”. In addition, the boundary between “semiconductor” and “insulator” is ambiguous and may not be strictly discriminated. Therefore, a “semiconductor” in this specification can be called an “insulator” in some cases. Similarly, an “insulator” in this specification can be called a “semiconductor” in some cases.

In addition, even when “semiconductor” is described, for example, when the conductivity is sufficiently high, the semiconductor device may have characteristics as a “conductor”. In addition, the boundary between “semiconductor” and “conductor” is ambiguous, and there are cases where it cannot be strictly distinguished. Therefore, a “semiconductor” in this specification can be called a “conductor” in some cases. Similarly, a “conductor” in this specification can be called a “semiconductor” in some cases.

Note that the impurity of the semiconductor means, for example, a component other than the main component constituting the semiconductor. For example, an element having a concentration of less than 0.1 atomic% is an impurity. When impurities are included, for example, DOS (Density of State) may be formed in the semiconductor, carrier mobility may be reduced, or crystallinity may be reduced. When the semiconductor is an oxide semiconductor, examples of impurities that change the characteristics of the semiconductor include Group 1 elements, Group 2 elements, Group 14 elements, Group 15 elements, and transition metals other than the main component. In particular, for example, hydrogen (also included in water), lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen and the like. In the case of an oxide semiconductor, oxygen vacancies may be formed by mixing impurities such as hydrogen, for example. In the case where the semiconductor is a silicon layer, examples of impurities that change the characteristics of the semiconductor include group 1 elements, group 2 elements, group 13 elements, and group 15 elements excluding oxygen and hydrogen.

In this specification, when it is described that A has a region having a concentration B, for example, when the entire depth direction in a region with A is a concentration B, the average value in the depth direction in a region with A Is the density B, the median value in the depth direction in the area with A is the density B, the maximum value in the depth direction in the area with A is the density B, the depth in the area with A The case where the minimum value in the direction is the density B, the convergence value in the depth direction in a certain area of A is the density B, and the area where a probable value of A itself is obtained in the measurement is the density B is included. .

In addition, in this specification, when A is described as having a region having a size B, a length B, a thickness B, a width B, or a distance B, for example, the entire region in which A is a size B, a length If the average value in a region of A is size B, length B, thickness B, width B, or distance B when the thickness is B, thickness B, width B, or distance B, in the region of A When the median is size B, length B, thickness B, width B, or distance B, the maximum value in a region of A is size B, length B, thickness B, width B, or distance B. In some cases, when the minimum value in a region of A is size B, length B, thickness B, width B, or distance B, the convergence value in a region of A is size B, length B, thickness In the case of B, width B, or distance B, the region where a probable value of A itself is obtained in measurement is size B, length B, thickness B, incl. Such as when the width B or distance B.

Note that the channel length refers to, for example, a region where a semiconductor (or a portion where current flows in the semiconductor when the transistor is on) and a gate electrode overlap with each other in a top view of the transistor, or a region where a channel is formed The distance between the source (source region or source electrode) and the drain (drain region or drain electrode) in FIG. Note that in one transistor, the channel length is not necessarily the same in all regions. That is, the channel length of one transistor may not be fixed to one value. Therefore, in this specification, the channel length is any one of values, the maximum value, the minimum value, or the average value in a region where a channel is formed.

The channel width is, for example, a region in which a semiconductor (or a portion in which a current flows in the semiconductor when the transistor is on) and a gate electrode overlap each other, or a source and a drain in a region where a channel is formed. This is the length of the part. Note that in one transistor, the channel width is not necessarily the same in all regions. That is, the channel width of one transistor may not be fixed to one value. Therefore, in this specification, the channel width is any one of values, the maximum value, the minimum value, or the average value in a region where a channel is formed.

Note that depending on the structure of the transistor, the channel width in a region where a channel is actually formed (hereinafter referred to as an effective channel width) and the channel width shown in a top view of the transistor (hereinafter, apparent channel width). May be different). For example, in a transistor having a three-dimensional structure, the effective channel width is larger than the apparent channel width shown in the top view of the transistor, and the influence may not be negligible. For example, in a transistor having a fine and three-dimensional structure, the ratio of the channel region formed on the side surface of the semiconductor may be larger than the ratio of the channel region formed on the upper surface of the semiconductor. In that case, the effective channel width in which the channel is actually formed is larger than the apparent channel width shown in the top view.

By the way, in a transistor having a three-dimensional structure, it may be difficult to estimate an effective channel width by actual measurement. For example, in order to estimate the effective channel width from the design value, it is necessary to assume that the shape of the semiconductor is known. Therefore, it is difficult to accurately measure the effective channel width when the shape of the semiconductor is not accurately known.

Therefore, in this specification, in the top view of a transistor, an apparent channel width which is a length of a portion where a source and a drain face each other in a region where a semiconductor and a gate electrode overlap with each other is expressed as “enclosed channel width ( SCW: Surrounded Channel Width). In this specification, in the case where the term “channel width” is simply used, it may denote an enclosed channel width or an apparent channel width. Alternatively, in this specification, in the case where the term “channel width” is simply used, it may denote an effective channel width. Note that the channel length, channel width, effective channel width, apparent channel width, enclosed channel width, and the like can be determined by obtaining a cross-sectional TEM image and analyzing the image. it can.

Note that in the case where the field-effect mobility of a transistor, the current value per channel width, and the like are calculated and calculated, the calculation may be performed using the enclosed channel width. In that case, the value may be different from that calculated using the effective channel width.

Note that in this specification, when A is described as having a shape protruding from B, in a top view or a cross-sectional view, it indicates that at least one end of A has a shape that is outside of at least one end of B. There is a case. Therefore, when it is described that A has a shape protruding from B, for example, in a top view, it can be read that one end of A has a shape outside of one end of B.

In this specification, “parallel” refers to a state in which two straight lines are arranged at an angle of −10 ° to 10 °. Therefore, the case of −5 ° to 5 ° is also included. Further, “substantially parallel” means a state in which two straight lines are arranged at an angle of −30 ° to 30 °. “Vertical” refers to a state in which two straight lines are arranged at an angle of 80 ° to 100 °. Therefore, the case of 85 ° to 95 ° is also included. Further, “substantially vertical” means a state in which two straight lines are arranged at an angle of 60 ° to 120 °.

In this specification, when a crystal is trigonal or rhombohedral, it is represented as a hexagonal system.

<Semiconductor Device> A semiconductor device according to one embodiment of the present invention will be described below.

FIG. 1 is a cross-sectional view illustrating a method for manufacturing a semiconductor device.

First, the substrate 102 and the layer 105 over the substrate 102 are prepared (see FIG. 1A).

As the substrate 102, for example, an insulator substrate, a semiconductor substrate, or a conductor substrate may be used.

The layer 105 is preferably formed using an insulator or a semiconductor that can be selected by etching with respect to the substrate 102. In the subsequent step, an oxide is preferably used for the layer 105 so that the layer 105 does not react with oxygen. For example, the layer 105 includes titanium oxide, manganese oxide, zinc oxide, gallium oxide, molybdenum oxide, indium oxide, tin oxide, tungsten oxide, In—Ga oxide, In—Zn oxide, Zn—Ga oxide, Zn -Sn oxide, In-Ga-Zn oxide, In-Sn-Zn oxide, In-Hf-Zn oxide, or the like may be used. In particular, in an atomic ratio, an In—Ga—Zn oxide having more Ga than In, an In—Ga—Zn oxide having Ga more than twice that of In, or Ga more than three times that of In It is preferable to use an In—Ga—Zn oxide.

Next, treatment for adding oxygen to the layer 105 is performed while the substrate 102 is heated. FIG. 1B shows an example in which oxygen ions 120 are added by an ion implantation method. The substrate heats the substrate 102 using the heater 103. FIG. 1B shows an example of a vertical substrate type apparatus. In this specification, making the substrate surface an angle close to perpendicular to the horizontal plane (70 degrees or more and 110 degrees or less) is referred to as vertical placement of the substrate. The means for heating the substrate 102 is not limited to the heater 103 incorporated in the substrate holding member 101, and any heating means capable of performing uniform heating in a short time may be used. For example, a lamp may be used instead of the heater 103.

Note that one embodiment of the present invention is not limited to this method. For example, oxygen can be added to the layer 105 by treatment with plasma containing oxygen. The plasma treatment may be performed by applying a bias voltage toward the substrate 102. By applying a bias voltage, oxygen can be efficiently added.

The ion implantation method includes a method using ions separated by mass and a method using ions not mass-separated. By using ions subjected to mass separation, mixing of impurities into the layer 105 can be reduced. In addition, variation in the amount of ions added can be reduced. On the other hand, a large amount of ions can be added in a short time by using ions that are not mass separated.

Oxygen is added while heating. The added oxygen diffuses in the layer 105 and the like by heating. Therefore, oxygen can be added without unevenness. In addition, since bias is reduced, oxygen can be added efficiently. The heating temperature is, for example, 60 ° C. or more and 500 ° C. or less, preferably 250 ° C. or more and 450 ° C. or less.

The oxygen ions 120 are not limited to monoatomic ions. For example, molecular ions containing oxygen such as O ₂ ions, O ₃ ions, CO ₂ ions, N ₂ O ions, NO ₂ ions, and NO ions may be used. Molecular ions have a larger mass than monoatomic ions. Therefore, when ion implantation is performed at the same acceleration voltage, oxygen is implanted into a region where molecular ions are shallower than monoatomic ions. In other words, since ions are not implanted deeply even at a high acceleration voltage, a large amount of oxygen can be added in a short time.

By adding the oxygen ions 120 to the layer 105, excess oxygen 132 is generated in the layer 105 (see FIG. 1C).

Next, a semiconductor element using the layer 105 can be manufactured. A method for manufacturing the semiconductor element will be described later.

<Transistor 1> A transistor according to one embodiment of the present invention is described below.

2A, 3A, 4A, 5A, and 6A are top views illustrating a method for manufacturing a transistor. In each top view, an alternate long and short dash line A1-A2 and an alternate long and short dash line A3-A4 are shown, and cross-sectional views corresponding thereto are shown in FIGS. 2B, 3B, 4B, and 5B. And shown in FIG.

First, the substrate 400 is prepared.

As the substrate 400, for example, an insulator substrate, a semiconductor substrate, or a conductor substrate may be used. Examples of the insulator substrate include a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as a yttria stabilized zirconia substrate), and a resin substrate. Examples of the semiconductor substrate include a single semiconductor substrate such as silicon or germanium, or a semiconductor substrate such as silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Furthermore, there is a semiconductor substrate having an insulator region inside the semiconductor substrate, for example, an SOI (Silicon On Insulator) substrate. Examples of the conductor substrate include a graphite substrate, a metal substrate, an alloy substrate, and a conductive resin substrate. Alternatively, there are a substrate having a metal nitride, a substrate having a metal oxide, and the like. Further, there are a substrate in which a conductor or a semiconductor is provided on an insulator substrate, a substrate in which a conductor or an insulator is provided on a semiconductor substrate, a substrate in which a semiconductor or an insulator is provided on a conductor substrate, and the like. Alternatively, a substrate in which an element is provided may be used. Examples of the element provided on the substrate include a capacitor element, a resistor element, a switch element, a light emitting element, and a memory element.

As the substrate 400, a flexible substrate that can withstand the substrate temperature at the time of doping may be used. Note that as a method for providing a transistor over a flexible substrate, there is a method in which after a transistor is manufactured over a non-flexible substrate, the transistor is peeled off and transferred to the substrate 400 which is a flexible substrate. In that case, a separation layer is preferably provided between the non-flexible substrate and the transistor. Note that a sheet, a film, a foil, or the like in which fibers are knitted may be used as the substrate 400. Further, the substrate 400 may have elasticity. Further, the substrate 400 may have a property of returning to the original shape when bending or pulling is stopped. Or you may have a property which does not return to an original shape. The thickness of the substrate 400 is, for example, 5 μm to 700 μm, preferably 10 μm to 500 μm, and more preferably 15 μm to 300 μm. When the substrate 400 is thinned, the weight of the semiconductor device can be reduced. Further, by making the substrate 400 thin, it may have elasticity even when glass or the like is used, or may have a property of returning to its original shape when bending or pulling is stopped. Therefore, an impact applied to the semiconductor device on the substrate 400 due to a drop or the like can be reduced. That is, a durable semiconductor device can be provided.

As the substrate 400 which is a flexible substrate, for example, a metal, an alloy, a resin, glass, or fiber thereof can be used. The substrate 400, which is a flexible substrate, is preferable because the deformation due to the environment is suppressed as the linear expansion coefficient is lower. For example, a material having a linear expansion coefficient of 1 × 10 ⁻³ / K or less, 5 × 10 ⁻⁵ / K or less, or 1 × 10 ⁻⁵ / K or less is used as the substrate 400 that is a flexible substrate. Good. Examples of the resin include polyester, polyolefin, polyamide (such as nylon and aramid), polyimide, polycarbonate, and acrylic. In particular, since aramid has a low coefficient of linear expansion, it is suitable as the substrate 400 that is a flexible substrate.

Next, a conductor is formed. The conductive film is formed by sputtering, chemical vapor deposition (CVD), molecular beam epitaxy (MBE) or pulsed laser deposition (PLD), atomic layer deposition. The method (ALD: Atomic Layer Deposition) can be used.

The CVD method can be classified into a plasma CVD (PECVD: Plasma Enhanced CVD) method using plasma, a thermal CVD (TCVD: Thermal CVD) method using heat, a photo CVD (Photo CVD) method using light, and the like. . Further, it can be classified into a metal CVD (MCVD: Metal CVD) method and an organic metal CVD (MOCVD: Metal Organic CVD) method depending on the source gas used.

The PECVD method can obtain a high quality film at a relatively low temperature. The TCVD method is a film formation method that can reduce plasma damage to an object to be processed because plasma is not used. For example, a wiring, an electrode, an element (a transistor, a capacitor, or the like) included in the semiconductor device may be charged up by receiving electric charge from plasma. At this time, a wiring, an electrode, an element, or the like included in the semiconductor device may be destroyed by the accumulated charge. On the other hand, in the case of a TCVD method that does not use plasma, such plasma damage does not occur, so that the yield of semiconductor devices can be increased. Further, in the TCVD method, plasma damage during film formation does not occur, so that a film with few defects can be obtained.

The ALD method is also a film forming method that can reduce plasma damage to an object to be processed. In addition, since the ALD method does not cause plasma damage during film formation, a film with few defects can be obtained.

The CVD method and the ALD method are film forming methods in which a film is formed by a reaction on the surface of an object to be processed, unlike a film forming method in which particles emitted from a target or the like are deposited. Therefore, it is a film forming method that is not easily affected by the shape of the object to be processed and has good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, and thus is suitable for covering the surface of an opening having a high aspect ratio. However, since the ALD method has a relatively low film formation rate, it may be preferable to use it in combination with another film formation method such as a CVD method with a high film formation rate.

In the CVD method and the ALD method, the composition of the obtained film can be controlled by the flow rate ratio of the source gases. For example, in the CVD method and the ALD method, a film having an arbitrary composition can be formed depending on the flow rate ratio of the source gases. Further, for example, in the CVD method and the ALD method, a film whose composition is continuously changed can be formed by changing the flow rate ratio of the source gas while forming the film. When film formation is performed while changing the flow rate ratio of the source gas, the time required for film formation can be shortened by the time required for conveyance and pressure adjustment compared to the case where film formation is performed using a plurality of film formation chambers. it can. Therefore, the productivity of the semiconductor device may be increased.

Next, a resist or the like is formed over the conductor and processed using the resist, so that the conductor 413 is formed. Note that the case of simply forming a resist includes the case of forming an antireflection layer under the resist.

The resist is removed after the object is processed by etching or the like. For the removal of the resist, plasma treatment and / or wet etching is used. Note that plasma ashing is preferable as the plasma treatment. If the removal of the resist or the like is insufficient, the remaining resist or the like may be removed with hydrofluoric acid or / and ozone water having a concentration of 0.001 volume% or more and 1 volume% or less.

Examples of the conductor to be the conductor 413 include boron, nitrogen, oxygen, fluorine, silicon, phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel, copper, zinc, gallium, yttrium, zirconium, molybdenum, ruthenium, A conductor including one or more of silver, indium, tin, tantalum, and tungsten may be used in a single layer or a stacked layer. For example, it may be an alloy or a compound, a conductor containing aluminum, a conductor containing copper and titanium, a conductor containing copper and manganese, a conductor containing indium, tin and oxygen, a conductor containing titanium and nitrogen Etc. may be used.

Next, the insulator 402 is formed (see FIGS. 2A and 2B). The insulator 402 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

As the insulator 402, for example, an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum is used. Or a single layer or a stacked layer. For example, as the insulator 402, aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or oxide Tantalum may be used.

The insulator 402 is preferably an insulator having excess oxygen and / or a hydrogen trap.

An insulator having excess oxygen is 1 × 10 ¹⁸ atoms / cm ^{3 in} a surface temperature range of 100 ° C. or higher and 700 ° C. or lower or 100 ° C. or higher and 500 ° C. or lower by thermal desorption gas spectroscopy analysis (TDS analysis). As described above, oxygen (converted to the number of oxygen atoms) of 1 × 10 ¹⁹ atoms / cm ³ or more or 1 × 10 ²⁰ atoms / cm ³ or more may be released.

A method for measuring the amount of released oxygen using TDS analysis will be described below.

The total amount of gas released when the measurement sample is subjected to TDS analysis is proportional to the integrated value of the ionic strength of the released gas. The total amount of gas released can be calculated by comparison with a standard sample.

For example, from the TDS analysis result of a silicon substrate containing a predetermined density of hydrogen, which is a standard sample, and the TDS analysis result of the measurement sample, the amount of released oxygen molecules (N _O2 ) of the measurement sample is obtained by the following formula: Can do. Here, it is assumed that all the gases detected by the mass-to-charge ratio 32 obtained by TDS analysis are derived from oxygen molecules. The mass to charge ratio of CH ₃ OH is 32 but is not considered here as it is unlikely to exist. In addition, oxygen molecules containing oxygen atoms with a mass number of 17 and oxygen atoms with a mass number of 18 which are isotopes of oxygen atoms are not considered because the existence ratio in nature is extremely small.

N _O2 = N _H2 / S _H2 × S _O2 × α

N _H2 is a value obtained by converting hydrogen molecules desorbed from the standard sample by density. _SH2 is an integral value of ion intensity when the standard sample is subjected to TDS analysis. Here, the reference value of the standard sample is N _H2 / SH ₂ . S _O2 is an integrated value of ion intensity when the measurement sample is subjected to TDS analysis. α is a coefficient that affects the ionic strength in the TDS analysis. For details of the above formula, refer to JP-A-6-275697. The amount of released oxygen is measured using a temperature-programmed desorption analyzer EMD-WA1000S / W manufactured by Electronic Science Co., Ltd. and using a silicon substrate containing a certain amount of hydrogen atoms as a standard sample.

In TDS analysis, part of oxygen is detected as oxygen atoms. The ratio of oxygen molecules to oxygen atoms can be calculated from the ionization rate of oxygen molecules. Note that since the above α includes the ionization rate of oxygen molecules, the amount of released oxygen atoms can be estimated by evaluating the amount of released oxygen molecules.

Note that N _{2 O 2} is the amount of released oxygen molecules. The amount of release when converted to oxygen atoms is twice the amount of release of oxygen molecules.

Alternatively, the insulator from which oxygen is released by heat treatment may contain a peroxide radical. Specifically, it means that the spin density resulting from the peroxide radical is 5 × 10 ¹⁷ spins / cm ³ or more. Note that an insulator containing a peroxide radical may have an asymmetric signal with a g value near 2.01 by an electron spin resonance (ESR) method.

The insulator 402 may have a function of preventing diffusion of impurities from the substrate 400.

Next, excess oxygen and a hydrogen trap may be included in the insulator 402 by adding oxygen ions or fluorine ions to the insulator 402 while heating the substrate to 60 ° C to 500 ° C. The reason why excess oxygen and hydrogen traps are formed by the addition of fluorine ions will be described later. Oxygen ions may be added by, for example, an ion implantation method with an acceleration voltage of 0.2 kV to 250 kV and a dose of 1 × 10 ¹¹ ions / cm ^{2 to} 5 × 10 ¹⁶ ions / cm ² . Fluorine ions are added by, for example, an ion implantation method with an acceleration voltage of 2 kV to 100 kV, preferably 5 kV to 50 kV, and a dose of 1 × 10 ¹⁴ ions / cm ^{2 to} 5 × 10 ¹⁶ ions / cm ^2. Preferably, it may be performed at 5 × 10 ¹⁴ ions / cm ² or more and 1 × 10 ¹⁶ ions / cm ² or less.

Next, a semiconductor to be the semiconductor 406a is formed. The semiconductor to be the semiconductor 406a can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

Next, excess oxygen may be included in the semiconductor to be the semiconductor 406a by adding oxygen ions while the substrate is heated. Oxygen ions may be added by, for example, ion implantation with an acceleration voltage of 0.2 kV to 250 kV and a dose of 1 × 10 ¹¹ ions / cm ^{2 to} 5 × 10 ¹⁶ ions / cm ² . By adding oxygen ions while the substrate is heated, damage during addition of oxygen ions can be suppressed and the crystallinity of the semiconductor 406a can be maintained. When many oxygen ions are added without heating, a spinel phase may be formed in the semiconductor 406a. When a spinel phase is formed in the semiconductor 406a, the crystallinity of the semiconductor (406b) formed on the semiconductor 406a is also affected, so that a spinel phase may be formed in the semiconductor 406b. Leading to a decline. Therefore, it is useful to contain excess oxygen in the film by ion implantation while maintaining the crystallinity and heating the substrate.

Next, a semiconductor to be the semiconductor 406b is formed. The semiconductor to be the semiconductor 406b can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Note that the formation of the semiconductor to be the semiconductor 406a and the formation of the semiconductor to be the semiconductor 406b are continuously performed without being exposed to the air, so that contamination of impurities into the film and the interface can be reduced. .

Next, it is preferable to perform a heat treatment. By performing heat treatment, the hydrogen concentration of the semiconductor to be the semiconductor 406a and the semiconductor to be the semiconductor 406b can be reduced in some cases. In some cases, oxygen vacancies in the semiconductor to be the semiconductor 406a and the semiconductor to be the semiconductor 406b can be reduced. The heat treatment may be performed at 250 ° C to 650 ° C, preferably 450 ° C to 600 ° C, more preferably 520 ° C to 570 ° C. The heat treatment is performed in an inert gas atmosphere or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. The heat treatment may be performed in a reduced pressure state. Alternatively, the heat treatment may be performed in an atmosphere containing an oxidizing gas of 10 ppm or more, 1% or more, or 10% or more in order to supplement the desorbed oxygen after the heat treatment in an inert gas atmosphere. By the heat treatment, crystallinity of the semiconductor to be the semiconductor 406a and the semiconductor to be the semiconductor 406b can be increased, impurities such as hydrogen and water can be removed, and the like. For the heat treatment, an RTA apparatus using lamp heating can also be used.

Next, a resist or the like is formed over the semiconductor to be the semiconductor 406b and processed using the resist, so that the semiconductor 406b and the semiconductor 406a are formed (see FIGS. 3A and 3B).

Next, a conductor is formed. The conductor can be formed by sputtering, CVD, MBE, PLD, ALD, or the like.

Examples of the conductor include boron, nitrogen, oxygen, fluorine, silicon, phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel, copper, zinc, gallium, yttrium, zirconium, molybdenum, ruthenium, silver, indium and tin. A conductor containing one or more of tantalum and tungsten may be used in a single layer or a stacked layer. For example, it may be an alloy or a compound, a conductor containing aluminum, a conductor containing copper and titanium, a conductor containing copper and manganese, a conductor containing indium, tin and oxygen, a conductor containing titanium and nitrogen Etc. may be used.

Next, a resist or the like is formed over the conductor and processed using the resist, so that the conductor 416a and the conductor 416b are formed (see FIGS. 4A and 4B).

For example, when the conductor 413 is a gate electrode, the insulator 402 is a gate insulator, the conductor 416a is a source electrode, and the conductor 416b is a drain electrode, the process is completed up to FIG. 4 and the transistor has a bottom gate structure. Also good.

Next, a semiconductor 436c is formed. The semiconductor 436c can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The surfaces of the semiconductor 406a, the semiconductor 406b, the conductor 416a, and the conductor 416b may be etched before the formation of the semiconductor 436c. For example, etching can be performed using plasma containing a rare gas. After that, the semiconductor 436c is continuously formed without being exposed to the air, so that impurities can be prevented from entering the interface between the semiconductor 406a, the semiconductor 406b, the conductor 416a, the conductor 416b, and the semiconductor 436c. it can. Impurities existing at the interface between the films may diffuse more easily than the impurities in the film. Therefore, stable electrical characteristics can be imparted to the transistor by reducing mixing of the impurities.

Next, the insulator 442 is formed. The insulator 442 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Note that the formation of the semiconductor 436c and the insulator 442 can be successively performed without being exposed to the air, so that contamination of impurities into the film and the interface can be reduced.

As the insulator 442, for example, an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum is used. Or a single layer or a stacked layer. For example, as the insulator 442, aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or oxide Tantalum may be used.

Next, excess oxygen and a hydrogen trap may be included in the insulator 442 by adding fluorine ions or oxygen ions while the substrate is heated.

Through the above steps, the transistor according to one embodiment of the present invention can be manufactured.

In the transistor illustrated in FIG. 6B, the insulator 402 and / or the insulator 442 and the like have excess oxygen and hydrogen traps. Through these actions, oxygen vacancies or hydrogen in the semiconductor 406a, the semiconductor 406b, and the semiconductor 436c can be reduced. That is, a transistor having excellent electrical characteristics can be provided. Further, the inclusion of fluorine in the insulator 402 and / or the insulator 442 improves the withstand voltage of the FET.

6B, the semiconductor 406b can be electrically surrounded by the electric fields of the conductor 404 and the conductor 413 (the structure of the transistor that electrically surrounds the semiconductor by the electric field generated from the conductor is (Surrounded channel (s-channel) structure). Therefore, a channel is formed in the entire semiconductor (upper surface, lower surface and side surfaces). In the s-channel structure, a large current can flow between the source and the drain of the transistor, and a current (on-state current) during conduction can be increased.

Note that in the case where the transistor has an s-channel structure, a channel is also formed on the side surface of the semiconductor 406b. Accordingly, the thicker the semiconductor 406b, the larger the channel region. That is, the thicker the semiconductor 406b, the higher the on-state current of the transistor. In addition, the thicker the semiconductor 406b, the higher the ratio of regions with high carrier controllability, so that the subthreshold swing value can be reduced. For example, the semiconductor 406b may have a thickness of 20 nm or more, preferably 40 nm or more, more preferably 60 nm or more, and more preferably 100 nm or more. However, since the productivity of the semiconductor device may be reduced, the semiconductor 406b having a region with a thickness of 300 nm or less, preferably 200 nm or less, and more preferably 150 nm or less may be used.

Since a high on-state current can be obtained, the s-channel structure can be said to be a structure suitable for a miniaturized transistor. Since a transistor can be miniaturized, a semiconductor device including the transistor can be a highly integrated semiconductor device with high integration. For example, the transistor has a region with a channel length of preferably 40 nm or less, more preferably 30 nm or less, more preferably 20 nm or less, and the transistor has a channel width of preferably 40 nm or less, more preferably 30 nm or less, and more. Preferably, it has a region of 20 nm or less.

Note that the conductor 413 is not necessarily formed (see FIG. 7A). Alternatively, the insulator 442 and the semiconductor 436c may protrude from the conductor 404 (see FIG. 7B). Further, the insulator 442 and the semiconductor 436c are not necessarily processed (see FIG. 7C). Further, the width of the conductor 413 in the A1-A2 cross section may be larger than that of the semiconductor 406b (see FIG. 8A). The conductor 413 and the conductor 404 may be in contact with each other through an opening (see FIG. 8B). The conductor 404 is not necessarily provided (see FIG. 8C). .

<Semiconductor> The electrical characteristics of the transistor may be improved by placing the semiconductor 406a and the semiconductor 436c above and below the semiconductor 406b.

The semiconductor 406b is an oxide semiconductor containing indium, for example. For example, when the semiconductor 406b contains indium, the carrier mobility (electron mobility) increases. The semiconductor 406b preferably contains an element M. The element M preferably represents Ti, Ga, Y, Zr, La, Ce, Nd, Sn or Hf. However, the element M may be a combination of a plurality of the aforementioned elements. The element M is an element having a high binding energy with oxygen, for example. For example, it is an element whose binding energy with oxygen is higher than that of indium. Alternatively, the element M is an element having a function of increasing the energy gap of the oxide semiconductor, for example. The semiconductor 406b preferably contains zinc. An oxide semiconductor may be easily crystallized when it contains zinc.

Note that the semiconductor 406b is not limited to the oxide semiconductor containing indium. The semiconductor 406b may be an oxide semiconductor containing zinc, an oxide semiconductor containing gallium, an oxide semiconductor containing tin, or the like that does not contain indium, such as zinc tin oxide and gallium tin oxide.

For the semiconductor 406b, an oxide with a wide energy gap is used, for example. The energy gap of the semiconductor 406b is, for example, 2.5 eV to 4.2 eV, preferably 2.8 eV to 3.8 eV, and more preferably 3 eV to 3.5 eV.

For example, the semiconductor 406a and the semiconductor 436c are oxide semiconductors including one or more elements other than oxygen included in the semiconductor 406b or two or more elements. Since the semiconductor 406a and the semiconductor 436c are formed of one or more elements other than oxygen constituting the semiconductor 406b, or two or more elements, defect states are formed at the interface between the semiconductor 406a and the semiconductor 406b and at the interface between the semiconductor 406b and the semiconductor 436c. The position is difficult to form.

The semiconductor 406a, the semiconductor 406b, and the semiconductor 436c preferably contain at least indium. Note that when the semiconductor 406a is an In—M—Zn oxide and the sum of In and M is 100 atomic%, In is preferably less than 50 atomic%, M is higher than 50 atomic%, and more preferably In is less than 25 atomic%. , M is higher than 75 atomic%. In the case where the semiconductor 406b is an In—M—Zn oxide, when the sum of In and M is 100 atomic%, the In is preferably higher than 25 atomic%, the M is lower than 75 atomic%, and more preferably, In is higher than 34 atomic%. High, and M is less than 66 atomic%. In the case where the semiconductor 436c is an In—M—Zn oxide, when the sum of In and M is 100 atomic%, In is preferably less than 50 atomic%, M is higher than 50 atomic%, and more preferably In is less than 25 atomic%. , M is higher than 75 atomic%. Note that the semiconductor 436c may be formed using the same type of oxide as the semiconductor 406a. Note that the semiconductor 406a and / or the semiconductor 436c may not contain indium in some cases. For example, the semiconductor 406a and / or the semiconductor 436c may be gallium oxide. Note that the number of atoms of each element included in the semiconductor 406a, the semiconductor 406b, and the semiconductor 436c may not be a simple integer ratio.

As the semiconductor 406b, an oxide having an electron affinity higher than those of the semiconductor 406a and the semiconductor 436c is used. For example, as the semiconductor 406b, an oxide whose electron affinity is greater than or equal to 0.07 eV and less than or equal to 1.3 eV, preferably greater than or equal to 0.1 eV and less than or equal to 0.7 eV, more preferably greater than or equal to 0.15 eV and less than or equal to 0.4 eV, than the semiconductor 406a and the semiconductor 436c. Is used. Note that the electron affinity is the difference between the vacuum level and the energy at the bottom of the conduction band.

Note that indium gallium oxide has a small electron affinity and a high oxygen blocking property. Therefore, the semiconductor 436c preferably contains indium gallium oxide. The gallium atom ratio [Ga / (In + Ga)] is, for example, 70% or more, preferably 80% or more, and more preferably 90% or more.

At this time, when a gate voltage is applied, a channel is formed in the semiconductor 406b having high electron affinity among the semiconductors 406a, 406b, and 436c.

Here, a mixed region of the semiconductor 406a and the semiconductor 406b may be provided between the semiconductor 406a and the semiconductor 406b. Further, in some cases, there is a mixed region of the semiconductor 406b and the semiconductor 436c between the semiconductor 406b and the semiconductor 436c. The mixed region has a low density of defect states. Therefore, the stack of the semiconductor 406a, the semiconductor 406b, and the semiconductor 436c has a band diagram in which energy continuously changes (also referred to as a continuous junction) in the vicinity of each interface (see FIG. 9). Note that in some cases, the interfaces of the semiconductor 406a, the semiconductor 406b, and the semiconductor 436c cannot be clearly identified.

At this time, electrons move mainly in the semiconductor 406b, not in the semiconductor 406a and the semiconductor 436c. As described above, by reducing the defect level density at the interface between the semiconductor 406a and the semiconductor 406b and the defect level density at the interface between the semiconductor 406b and the semiconductor 436c, the movement of electrons in the semiconductor 406b is inhibited. And the on-state current of the transistor can be increased.

The on-state current of the transistor can be increased as the factor that hinders the movement of electrons is reduced. For example, when there is no factor that hinders the movement of electrons, it is estimated that electrons move efficiently. Electron movement is inhibited, for example, even when the physical unevenness of the channel formation region is large.

In order to increase the on-state current of the transistor, for example, the root mean square (RMS) roughness of the upper surface or the lower surface of the semiconductor 406b (formation surface, here, the semiconductor 406a) in the range of 1 μm × 1 μm is set. The thickness may be less than 1 nm, preferably less than 0.6 nm, more preferably less than 0.5 nm, and more preferably less than 0.4 nm. The average surface roughness (also referred to as Ra) in the range of 1 μm × 1 μm is less than 1 nm, preferably less than 0.6 nm, more preferably less than 0.5 nm, and more preferably less than 0.4 nm. The maximum height difference (also referred to as PV) in the range of 1 μm × 1 μm is less than 10 nm, preferably less than 9 nm, more preferably less than 8 nm, and more preferably less than 7 nm. The RMS roughness, Ra, and PV can be measured using a scanning probe microscope system SPA-500 manufactured by SII Nano Technology.

In order to increase the on-state current of the transistor, the thickness of the semiconductor 436c is preferably as small as possible. For example, the semiconductor 436c may have a region of less than 10 nm, preferably 5 nm or less, more preferably 3 nm or less. On the other hand, the semiconductor 436c has a function of blocking entry of elements other than oxygen (such as hydrogen and silicon) included in the adjacent insulator into the semiconductor 406b where a channel is formed. Therefore, the semiconductor 436c preferably has a certain thickness. For example, the semiconductor 436c may have a thickness of 0.3 nm or more, preferably 1 nm or more, and more preferably 2 nm or more. The semiconductor 436c preferably has a property of blocking oxygen in order to suppress outward diffusion of oxygen released from the insulator 402 and the like.

In order to increase reliability, the semiconductor 406a is preferably thick and the semiconductor 436c is preferably thin. For example, the semiconductor 406a may have a region with a thickness of 10 nm or more, preferably 20 nm or more, more preferably 40 nm or more, more preferably 60 nm or more. By increasing the thickness of the semiconductor 406a, the distance from the interface between the adjacent insulator and the semiconductor 406a to the semiconductor 406b where a channel is formed can be increased. However, since the productivity of the semiconductor device may be reduced, the semiconductor 406a having a region with a thickness of 200 nm or less, preferably 120 nm or less, and more preferably 80 nm or less may be used.

For example, between the semiconductor 406b and the semiconductor 406a, for example, in secondary ion mass spectrometry (SIMS), 1 × 10 ¹⁶ atoms / cm ³ or more and 1 × 10 ¹⁹ atoms / cm ³ or less, preferably Has a region having a silicon concentration of 1 × 10 ¹⁶ atoms / cm ³ or more and 5 × 10 ¹⁸ atoms / cm ³ or less, more preferably 1 × 10 ¹⁶ atoms / cm ³ or more and 2 × 10 ¹⁸ atoms / cm ³ or less. Further, between SIMS 406b and 436c, in SIMS, 1 × 10 ¹⁶ atoms / cm ³ or more and 1 × 10 ¹⁹ atoms / cm ³ or less, preferably 1 × 10 ¹⁶ atoms / cm ³ or more and 5 × 10 ¹⁸ atoms or less. / Cm ³ or less, more preferably a region having a silicon concentration of 1 × 10 ¹⁶ atoms / cm ³ or more and 2 × 10 ¹⁸ atoms / cm ³ or less.

In order to reduce the hydrogen concentration of the semiconductor 406b, it is preferable to reduce the hydrogen concentration of the semiconductor 406a and the semiconductor 436c. The semiconductor 406a and the semiconductor 436c each have a SIMS of 1 × 10 ¹⁶ atoms / cm ^{3 to} 2 × 10 ²⁰ atoms / cm ³ , preferably 1 × 10 ¹⁶ atoms / cm ^{3 to} 5 × 10 ¹⁹ atoms / cm ³ , More preferably, a region having a hydrogen concentration of 1 × 10 ¹⁶ atoms / cm ^{3 to} 1 × 10 ¹⁹ atoms / cm ³ is more preferably 1 × 10 ¹⁶ atoms / cm ^{3 to} 5 × 10 ¹⁸ atoms / cm ^3. Have. In order to reduce the nitrogen concentration of the semiconductor 406b, it is preferable to reduce the nitrogen concentrations of the semiconductor 406a and the semiconductor 436c. The semiconductor 406a and the semiconductor 436c each have a SIMS of 1 × 10 ¹⁵ atoms / cm ^{3 to} 5 × 10 ¹⁹ atoms / cm ³ , preferably 1 × 10 ¹⁵ atoms / cm ^{3 to} 5 × 10 ¹⁸ atoms / cm ³ , More preferably, a region having a nitrogen concentration of 1 × 10 ¹⁵ atoms / cm ^{3 to} 1 × 10 ¹⁸ atoms / cm ³ is more preferably 1 × 10 ¹⁵ atoms / cm ^{3 to} 5 × 10 ¹⁷ atoms / cm ^3. Have.

The above three-layer structure is an example. For example, a two-layer structure without the semiconductor 406a or the semiconductor 436c may be used. Alternatively, a four-layer structure including any one of the semiconductors exemplified as the semiconductor 406a, the semiconductor 406b, and the semiconductor 436c above or below the semiconductor 406a or above or below the semiconductor 436c may be employed. Alternatively, the n-layer structure includes any one of the semiconductors exemplified as the semiconductor 406a, the semiconductor 406b, and the semiconductor 436c in any two or more positions over the semiconductor 406a, under the semiconductor 406a, over the semiconductor 436c, and under the semiconductor 436c. (N is an integer of 5 or more).

<Regarding Structure of Oxide Semiconductor> The structure of an oxide semiconductor will be described below.

An oxide semiconductor is classified into a single crystal oxide semiconductor and a non-single-crystal oxide semiconductor. As examples of the non-single-crystal oxide semiconductor, a CAAC-OS (C Axis Crystalline Oxide Semiconductor), a polycrystalline oxide semiconductor, a microcrystalline oxide semiconductor, an amorphous oxide semiconductor, and the like can be given.

From another viewpoint, the oxide semiconductor is divided into an amorphous oxide semiconductor and a crystalline oxide semiconductor other than the amorphous oxide semiconductor. Examples of a crystalline oxide semiconductor include a single crystal oxide semiconductor, a CAAC-OS, a polycrystalline oxide semiconductor, and a microcrystalline oxide semiconductor.

<CAAC-OS> First, the CAAC-OS will be described. Note that the CAAC-OS can also be referred to as an oxide semiconductor including CANC (C-Axis aligned nanocrystals).

The CAAC-OS is one of oxide semiconductors having a plurality of c-axis aligned crystal parts (also referred to as pellets).

A plurality of pellets can be confirmed by observing a composite analysis image (also referred to as a high-resolution TEM image) of a bright-field image and a diffraction pattern of a CAAC-OS with a transmission electron microscope (TEM: Transmission Electron Microscope). . On the other hand, in the high-resolution TEM image, the boundary between pellets, that is, the crystal grain boundary (also referred to as grain boundary) cannot be clearly confirmed. Therefore, it can be said that the CAAC-OS does not easily lower the electron mobility due to the crystal grain boundary.

Hereinafter, a CAAC-OS observed with a TEM will be described. FIG. 37A shows a high-resolution TEM image of a cross section of the CAAC-OS which is observed from a direction substantially parallel to the sample surface. For observation of the high-resolution TEM image, a spherical aberration correction function was used. A high-resolution TEM image using the spherical aberration correction function is particularly referred to as a Cs-corrected high-resolution TEM image. Acquisition of a Cs-corrected high-resolution TEM image can be performed by, for example, an atomic resolution analytical electron microscope JEM-ARM200F manufactured by JEOL Ltd.

FIG. 37B shows a Cs-corrected high-resolution TEM image obtained by enlarging the region (1) in FIG. FIG. 37B shows that metal atoms are arranged in a layered manner in a pellet. The arrangement of each layer of metal atoms reflects unevenness on a surface (also referred to as a formation surface) or an upper surface where a CAAC-OS film is formed, and is parallel to the formation surface or upper surface of the CAAC-OS.

As shown in FIG. 37B, the CAAC-OS has a characteristic atomic arrangement. FIG. 37C shows a characteristic atomic arrangement with an auxiliary line. 37B and 37C, it can be seen that the size of one pellet is about 1 nm to 3 nm and the size of the gap generated by the inclination between the pellet and the pellet is about 0.8 nm. Therefore, the pellet can also be referred to as a nanocrystal (nc).

Here, based on the Cs-corrected high-resolution TEM image, the arrangement of the CAAC-OS pellets 5100 on the substrate 5120 is schematically shown, which is a structure in which bricks or blocks are stacked (FIG. 37D). reference.). A portion where an inclination is generated between the pellets observed in FIG. 37C corresponds to a region 5161 illustrated in FIG.

FIG. 38A shows a Cs-corrected high-resolution TEM image of the plane of the CAAC-OS observed from a direction substantially perpendicular to the sample surface. The Cs-corrected high-resolution TEM images obtained by enlarging the region (1), the region (2), and the region (3) in FIG. 38A are shown in FIGS. 38B, 38C, and 38D, respectively. Show. From FIG. 38B, FIG. 38C, and FIG. 38D, it can be confirmed that the metal atoms are arranged in a triangular shape, a quadrangular shape, or a hexagonal shape in the pellet. However, there is no regularity in the arrangement of metal atoms between different pellets.

Next, the CAAC-OS analyzed by X-ray diffraction (XRD: X-Ray Diffraction) will be described. For example, when structural analysis by an out-of-plane method is performed on a CAAC-OS including an InGaZnO ₄ crystal, a peak appears at a diffraction angle (2θ) of around 31 ° as illustrated in FIG. There is. Since this peak is attributed to the (009) plane of the InGaZnO ₄ crystal, the CAAC-OS crystal has c-axis orientation, and the c-axis is oriented in a direction substantially perpendicular to the formation surface or the top surface. It can be confirmed.

Note that in structural analysis of the CAAC-OS by an out-of-plane method, in addition to a peak where 2θ is around 31 °, a peak may also appear when 2θ is around 36 °. A peak at 2θ of around 36 ° indicates that a crystal having no c-axis alignment is included in part of the CAAC-OS. In a more preferable CAAC-OS, in the structural analysis by the out-of-plane method, 2θ has a peak in the vicinity of 31 °, and 2θ has no peak in the vicinity of 36 °.

On the other hand, when structural analysis is performed on the CAAC-OS by an in-plane method in which X-rays are incident from a direction substantially perpendicular to the c-axis, a peak appears at 2θ of around 56 °. This peak is attributed to the (110) plane of the InGaZnO ₄ crystal. In the case of CAAC-OS, even when 2θ is fixed at around 56 ° and analysis (φ scan) is performed while rotating the sample with the normal vector of the sample surface as the axis (φ axis), FIG. A clear peak does not appear as shown. In contrast, in the case of a single crystal oxide semiconductor of InGaZnO ₄ , when φ scan is performed with 2θ fixed at around 56 °, it belongs to a crystal plane equivalent to the (110) plane as shown in FIG. 6 peaks are observed. Therefore, structural analysis using XRD can confirm that the CAAC-OS has irregular orientations in the a-axis and the b-axis.

Next, a CAAC-OS analyzed by electron diffraction will be described. For example, when an electron beam with a probe diameter of 300 nm is incident on a CAAC-OS having an InGaZnO ₄ crystal in parallel to the sample surface, a diffraction pattern (a limited-field transmission electron diffraction pattern as shown in FIG. Say) may appear. This diffraction pattern includes spots caused by the (009) plane of the InGaZnO ₄ crystal. Therefore, electron diffraction shows that the pellets included in the CAAC-OS have c-axis alignment, and the c-axis is in a direction substantially perpendicular to the formation surface or the top surface. On the other hand, FIG. 40B shows a diffraction pattern obtained when an electron beam with a probe diameter of 300 nm is incident on the same sample in a direction perpendicular to the sample surface. A ring-shaped diffraction pattern is confirmed from FIG. Therefore, electron diffraction shows that the a-axis and the b-axis of the pellet included in the CAAC-OS have no orientation. Note that the first ring in FIG. 40B is considered to originate from the (010) plane and the (100) plane of the InGaZnO ₄ crystal. In addition, it is considered that the second ring in FIG. 40B is caused by the (110) plane or the like.

A CAAC-OS is an oxide semiconductor with a low density of defect states. Examples of defects in the oxide semiconductor include defects due to impurities and oxygen vacancies. Therefore, the CAAC-OS can also be referred to as an oxide semiconductor with a low impurity concentration. A CAAC-OS can also be referred to as an oxide semiconductor with few oxygen vacancies. A CAAC-OS with few impurities and oxygen vacancies is an oxide semiconductor with low carrier density. Specifically, the carrier density is less than 8 × 10 ¹¹ / cm ³ , preferably less than 1 × 10 ¹¹ / cm ³ , more preferably less than 1 × 10 ¹⁰ / cm ³ , and 1 × 10 ⁻⁹ / cm ^3. This can be done. Such an oxide semiconductor is referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. The CAAC-OS has a low impurity concentration and a low density of defect states. That is, it can be said that the oxide semiconductor has stable characteristics.

An impurity contained in the oxide semiconductor might serve as a carrier trap or a carrier generation source. In addition, oxygen vacancies in the oxide semiconductor may serve as carrier traps or may serve as carrier generation sources by capturing hydrogen.

Note that the impurity means an element other than the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, or a transition metal element. For example, an element such as silicon, which has a stronger bonding force with oxygen than a metal element included in an oxide semiconductor, disturbs the atomic arrangement of the oxide semiconductor by depriving the oxide semiconductor of oxygen, thereby reducing crystallinity. It becomes a factor. In addition, heavy metals such as iron and nickel, argon, carbon dioxide, and the like have large atomic radii (or molecular radii), which disturbs the atomic arrangement of the oxide semiconductor and decreases crystallinity.

A highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor has few carrier traps. The charge trapped in the carrier trap of the oxide semiconductor takes a long time to be released and may behave as if it were a fixed charge. Therefore, a transistor including an oxide semiconductor with a high impurity concentration and a high density of defect states may have unstable electrical characteristics. On the other hand, a transistor using a CAAC-OS has a small change in electrical characteristics and has high reliability.

In addition, since the CAAC-OS has a low defect level density, carriers generated by light irradiation or the like are rarely trapped in the defect level. Therefore, a transistor using the CAAC-OS has little change in electrical characteristics due to irradiation with visible light or ultraviolet light.

<Microcrystalline Oxide Semiconductor> Next, a microcrystalline oxide semiconductor will be described.

A microcrystalline oxide semiconductor has a region where a crystal part can be confirmed and a region where a clear crystal part cannot be confirmed in a high-resolution TEM image. In most cases, a crystal part included in the microcrystalline oxide semiconductor has a size of 1 nm to 100 nm, or 1 nm to 10 nm. In particular, an oxide semiconductor including a nanocrystal that is a microcrystal of 1 nm to 10 nm, or 1 nm to 3 nm is referred to as an nc-OS (nanocrystalline Oxide Semiconductor). For example, the nc-OS may not be able to clearly confirm a crystal grain boundary in a high-resolution TEM image. Note that the nanocrystal may have the same origin as the pellet in the CAAC-OS. Therefore, the crystal part of nc-OS is sometimes referred to as a pellet below.

The nc-OS has periodicity in atomic arrangement in a minute region (for example, a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In addition, the nc-OS has no regularity in crystal orientation between different pellets. Therefore, orientation is not seen in the whole film. Therefore, the nc-OS may not be distinguished from an amorphous oxide semiconductor depending on an analysis method. For example, when structural analysis is performed on the nc-OS using an XRD apparatus using X-rays having a diameter larger than that of the pellet, a peak indicating a crystal plane is not detected in the analysis by the out-of-plane method. Further, when electron diffraction (also referred to as limited-field electron diffraction) using an electron beam with a probe diameter (for example, 50 nm or more) larger than the pellet is performed on the nc-OS, a diffraction pattern such as a halo pattern is observed. . On the other hand, when nanobeam electron diffraction is performed on the nc-OS using an electron beam having a probe diameter that is close to the pellet size or smaller than the pellet size, spots are observed. Further, when nanobeam electron diffraction is performed on the nc-OS, a region with high luminance may be observed like a circle (in a ring shape). Furthermore, a plurality of spots may be observed in the ring-shaped region.

Thus, since the crystal orientation does not have regularity between pellets (nanocrystals), nc-OS has an oxide semiconductor having RANC (Random Aligned Nanocrystals) or NANC (Non-Aligned nanocrystals). It can also be called an oxide semiconductor.

The nc-OS is an oxide semiconductor that has higher regularity than an amorphous oxide semiconductor. Therefore, the nc-OS has a lower density of defect states than an amorphous oxide semiconductor. Note that the nc-OS does not have regularity in crystal orientation between different pellets. Therefore, the nc-OS has a higher density of defect states than the CAAC-OS. Note that an nc-OS film with higher regularity than an amorphous oxide semiconductor is obtained immediately after film formation.

<Amorphous Oxide Semiconductor> Next, an amorphous oxide semiconductor will be described.

An amorphous oxide semiconductor is an oxide semiconductor in which atomic arrangement in a film is irregular and does not have a crystal part. An example is an oxide semiconductor having an amorphous state such as quartz.

In an amorphous oxide semiconductor, a crystal part cannot be confirmed in a high-resolution TEM image.

When structural analysis using an XRD apparatus is performed on an amorphous oxide semiconductor, a peak indicating a crystal plane is not detected by analysis using an out-of-plane method. In addition, when electron diffraction is performed on an amorphous oxide semiconductor, a halo pattern is observed. Further, when nanobeam electron diffraction is performed on an amorphous oxide semiconductor, no spot is observed and only a halo pattern is observed.

Various views have been presented regarding the amorphous structure. For example, a structure having no order in the atomic arrangement may be referred to as a complete amorphous structure. In addition, a structure having ordering up to the nearest interatomic distance or the distance between the second adjacent atoms and having no long-range ordering may be referred to as an amorphous structure. Therefore, according to the strictest definition, an oxide semiconductor having order in the atomic arrangement cannot be called an amorphous oxide semiconductor. At least an oxide semiconductor having long-range order cannot be called an amorphous oxide semiconductor. Thus, for example, the CAAC-OS and the nc-OS cannot be referred to as an amorphous oxide semiconductor or a completely amorphous oxide semiconductor because of having a crystal part.

<Amorphous Like Oxide Semiconductor> Note that an oxide semiconductor may have a structure between the nc-OS and the amorphous oxide semiconductor. An oxide semiconductor having such a structure is particularly referred to as an amorphous-like oxide semiconductor (a-like OS).

In the a-like OS, a void (also referred to as a void) may be observed in a high-resolution TEM image. Moreover, in a high-resolution TEM image, it has the area | region which can confirm a crystal part clearly, and the area | region which cannot confirm a crystal part.

Since it has a void, the a-like OS has an unstable structure. Hereinafter, in order to show that the a-like OS has an unstable structure as compared with the CAAC-OS and the nc-OS, changes in the structure due to electron irradiation are shown.

As samples for electron irradiation, a-like OS (referred to as sample A), nc-OS (referred to as sample B), and CAAC-OS (referred to as sample C) are prepared. Each sample is an In—Ga—Zn oxide.

First, a high-resolution cross-sectional TEM image of each sample is acquired. It can be seen from the high-resolution cross-sectional TEM image that each sample has a crystal part.

The determination of which part is regarded as one crystal part may be performed as follows. For example, the unit cell of an InGaZnO ₄ crystal has a structure in which three In—O layers and six Ga—Zn—O layers have a total of nine layers stacked in the c-axis direction. Are known. The spacing between these adjacent layers is about the same as the lattice spacing (also referred to as d value) of the (009) plane, and the value is determined to be 0.29 nm from crystal structure analysis. Therefore, a portion where the interval between lattice fringes is 0.28 nm or more and 0.30 nm or less can be regarded as a crystal part of InGaZnO ₄ . Note that the lattice fringes correspond to the ab plane of the InGaZnO ₄ crystal.

FIG. 41 is an example in which the average size of the crystal parts (from 22 to 45) of each sample was investigated. However, the length of the lattice fringes described above is the size of the crystal part. From FIG. 41, it can be seen that in the a-like OS, the crystal part becomes larger according to the cumulative dose of electrons. Specifically, as shown by (1) in FIG. 41, the crystal portion (also referred to as the initial nucleus) which was about 1.2 nm in the initial stage of observation by TEM has a cumulative irradiation dose of 4.2. It can be seen that the film grows to a size of about 2.6 nm at × 10 ⁸ e ⁻ / nm ² . On the other hand, in the nc-OS and the CAAC-OS, there is no change in the size of the crystal part in the range of the cumulative electron dose from the start of electron irradiation to 4.2 × 10 ⁸ e ⁻ / nm ^2. I understand. Specifically, as indicated by (2) and (3) in FIG. 41, the crystal part sizes of the nc-OS and the CAAC-OS are about 1.4 nm, respectively, regardless of the cumulative electron dose. And about 2.1 nm.

As described above, in the a-like OS, a crystal part may be grown by electron irradiation. On the other hand, in the nc-OS and the CAAC-OS, the crystal part is hardly grown by electron irradiation. That is, it can be seen that the a-like OS has an unstable structure compared to the nc-OS and the CAAC-OS.

In addition, since it has a void, the a-like OS has a lower density than the nc-OS and the CAAC-OS. Specifically, the density of the a-like OS is 78.6% or more and less than 92.3% of the density of the single crystal having the same composition. Further, the density of the nc-OS and the density of the CAAC-OS are 92.3% or more and less than 100% of the density of the single crystal having the same composition. An oxide semiconductor that is less than 78% of the density of a single crystal is difficult to form.

For example, in an oxide semiconductor satisfying In: Ga: Zn = 1: 1: 1 [atomic ratio], the density of single crystal InGaZnO ₄ having a rhombohedral structure is 6.357 g / cm ³ . Thus, for example, in an oxide semiconductor that satisfies In: Ga: Zn = 1: 1: 1 [atomic ratio], the density of a-like OS is 5.0 g / cm ³ or more and less than 5.9 g / cm ^3. . For example, in the oxide semiconductor satisfying In: Ga: Zn = 1: 1: 1 [atomic ratio], the density of the nc-OS and the density of the CAAC-OS is 5.9 g / cm ³ or more and 6.3 g / less than cm ³ .

Note that there may be no single crystal having the same composition. In that case, the density corresponding to the single crystal in a desired composition can be estimated by combining single crystals having different compositions at an arbitrary ratio. What is necessary is just to estimate the density corresponding to the single crystal of a desired composition using a weighted average with respect to the ratio which combines the single crystal from which a composition differs. However, the density is preferably estimated by combining as few kinds of single crystals as possible.

As described above, oxide semiconductors have various structures and various properties. Note that the oxide semiconductor may be a stacked film including two or more of an amorphous oxide semiconductor, an a-like OS, a microcrystalline oxide semiconductor, and a CAAC-OS, for example.

<CAAC-OS Film Formation Method> An example of a CAAC-OS film formation method will be described below.

  FIG. 42 is a schematic diagram illustrating the inside of the film formation chamber. The CAAC-OS can be formed by a sputtering method.

  As shown in FIG. 42, the substrate 5220 and the target 5230 are arranged to face each other. There is plasma 5240 between the substrate 5220 and the target 5230. The plasma 5240 includes ions 5201 in which a sputter gas component is ionized.

  The ions 5201 are accelerated toward the target 5230, and the pellet 5200 that is pellet-like particles is peeled off by impacting the target 5230. At the same time, the particles 5203 made of atoms constituting the target 5230 are also peeled off. Then, the pellet 5200 and the particle 5203 are charged by receiving an electric charge in the plasma 5240.

  On the substrate 5220 is an oxide thin film 5206 that has already been deposited. When the pellets 5200 and the particles 5203 reach the oxide thin film 5206, they are deposited so as to avoid other pellets 5200. This is due to the repulsive force (repulsive force) caused by the surface of the pellet 5200 being charged with the same polarity (here, negative). Note that the substrate 5220 is heated, and the deposited pellets 5200 and particles 5203 cause migration on the surface of the substrate 5220.

  Therefore, the oxide thin film 5206 and the pellet 5200 over the substrate 5220 have a cross-sectional shape as illustrated in FIG.

  Note that the pellet 5200 has a shape in which the target 5230 is cleaved. For example, in an In-M-Zn oxide (M represents Ti, Ga, Y, Zr, La, Ce, Nd, Sn, or Hf), the cross-sectional shape illustrated in FIG. The upper surface shape shown in FIG.

<CAAC-OS and nc-OS Film Formation Model> Next, a CAAC-OS film formation model will be described in detail.

A distance d (also referred to as a target-substrate distance (T-S distance)) between the substrate 5220 and the target 5230 is 0.01 m or more and 1 m or less, preferably 0.02 m or more and 0.5 m or less. The film formation chamber is mostly filled with a film forming gas (for example, oxygen, argon, or a mixed gas containing oxygen at a ratio of 5% by volume or more), and is 0.01 Pa to 100 Pa, preferably 0.1 Pa to 10 Pa. Controlled. Here, by applying a voltage of a certain level or higher to the target 5230, discharge starts and plasma 5240 is confirmed. Note that a high-density plasma region is formed in the vicinity of the target 5230 by a magnetic field. In the high-density plasma region, ions 5201 are generated by ionizing the deposition gas. The ion 5201 is, for example, an oxygen cation (O ⁺ ) or an argon cation (Ar ⁺ ). Note that although not illustrated, a heating mechanism may be provided below the substrate 5220.

  Although not shown, the target 5230 is bonded to the backing plate. A plurality of magnets are arranged at positions facing the target 5230 via the backing plate. A sputtering method that uses a magnetic field to increase the deposition rate is called a magnetron sputtering method.

  The target 5230 has a polycrystalline structure having a plurality of crystal grains, and any one of the crystal grains includes a cleavage plane.

  The ions 5201 generated in the high-density plasma region are accelerated toward the target 5230 by the electric field and eventually collide with the target 5230. At this time, the pellet 5200 which is a flat or pellet-like sputtered particle peels from the cleavage plane. The cross section of the pellet 5200 is as shown in FIG. 43B, and the top surface is as shown in FIG. Note that the structure of the pellet 5200 may be distorted by the impact of the collision of the ions 5201.

  The pellet 5200 is a sputtered particle in the form of a flat plate or a pellet having a triangular plane, for example, a regular triangular plane. Alternatively, the pellet 5200 is a flat or pellet-like sputtered particle having a hexagonal plane, for example, a regular hexagonal plane. However, the shape of the pellet 5200 is not limited to a triangle or a hexagon. For example, there are cases where a plurality of triangles are combined. For example, there may be a quadrangle (for example, a rhombus) in which two triangles (for example, regular triangles) are combined.

  The thickness of the pellet 5200 is determined according to the type of deposition gas. For example, the pellet 5200 has a thickness of 0.4 nm to 1 nm, preferably 0.6 nm to 0.8 nm. For example, the pellet 5200 has a width of 1 nm to 3 nm, preferably 1.2 nm to 2.5 nm.

When the pellet 5200 passes through the plasma 5240, the surface may be negatively or positively charged. That is because, for example, the pellet 5200 receives a negative charge from O ^{2− in the} plasma 5240. As a result, oxygen atoms on the surface of the pellet 5200 may be negatively charged. In addition, the pellet 5200 may grow by being combined with indium, the element M, zinc, oxygen, or the like in the plasma 5240 when passing through the plasma 5240.

  The pellets 5200 and the particles 5203 that have passed through the plasma 5240 reach the surface of the substrate 5220. Note that part of the particles 5203 has a small mass and may be discharged to the outside by a vacuum pump or the like.

  When the particles 5203 have filled the pellets 5200, a layer having a thickness similar to that of the pellets 5200 is formed. That is, the nanocrystal pellets 5200 are initially included, and are integrated by growing on the substrate 5220. A new first pellet 5200 is deposited on the integrated layer. A second layer is then formed. Furthermore, by repeating this, a thin film structure having a laminated body is formed.

  Note that the manner in which the pellets 5200 are deposited also varies depending on the surface temperature of the substrate 5220 and the like. For example, when the surface temperature of the substrate 5220 is high, the pellet 5200 undergoes migration on the surface of the substrate 5220. As a result, the proportion of the pellet 5200 and another pellet 5200 that are connected without the particle 5203 interposed therebetween increases, so that a CAAC-OS with high orientation is obtained. The surface temperature of the substrate 5220 in forming the CAAC-OS is 100 ° C. or higher and lower than 500 ° C., preferably 140 ° C. or higher and lower than 450 ° C., more preferably 170 ° C. or higher and lower than 400 ° C. Therefore, it can be seen that even when a large-area substrate of the eighth generation or higher is used as the substrate 5220, warping or the like hardly occurs.

  On the other hand, when the surface temperature of the substrate 5220 is low, the pellet 5200 is less likely to cause migration on the surface of the substrate 5220. As a result, the pellets 5200 are stacked to form an nc-OS with low orientation (see FIG. 44). In the nc-OS, since the pellet 5200 is negatively charged, the pellet 5200 may be deposited at an equal distance. Therefore, although the orientation is low, a slight regularity results in a dense structure as compared with an amorphous oxide semiconductor.

  In addition, one large pellet may be formed because the gap between the pellets is extremely small. The inside of one large pellet has a single crystal structure. For example, the size of the pellet may be 10 nm to 200 nm, 15 nm to 100 nm, or 20 nm to 50 nm when viewed from above.

  It is considered that the pellet 5200 is deposited on the surface of the substrate 5220 by the film formation model as described above. Even when the formation surface does not have a crystal structure, a CAAC-OS film can be formed, which indicates that the growth mechanism is different from that of epitaxial growth. The CAAC-OS and the nc-OS can form a film evenly even when the glass substrate has a large area. For example, the CAAC-OS can be formed even when the surface of the substrate 5220 (formation surface) has an amorphous structure (eg, amorphous silicon oxide).

  Further, it can be seen that even when the surface of the substrate 5220 which is the formation surface is uneven, the pellets 5200 are arranged along the shape.

With the deposition model described above, a CAAC-OS having high crystallinity can be obtained even on a formation surface having an amorphous structure. Note that a CAAC-OS having high crystallinity is obtained immediately after film formation.

<Silicon oxide having fluorine> Hereinafter, silicon oxide having fluorine which is an example of an insulator having excess oxygen and / or a hydrogen trap will be described with reference to FIGS.

Assume silicon oxide (SiO ₂ ) having two oxygen atoms per one silicon atom. As shown in FIG. 49A, one silicon atom is bonded to four oxygen atoms. One oxygen atom is bonded to two silicon atoms.

When two fluorine atoms enter silicon oxide, one oxygen atom bonded to the two silicon atoms is disconnected (... Si-O-Si ... + 2F → ... Si--O--Si. ... + 2F). Then, the fluorine atom and the silicon atom in which the bond with the oxygen atom is broken are combined (... Si--O--Si ... + 2F.fwdarw .... Si-FF-Si ... + O). At this time, the broken oxygen atom becomes excess oxygen (see FIG. 49B).

Oxygen vacancies in the oxide semiconductor can be reduced by excess oxygen contained in silicon oxide. Oxygen deficiency in an oxide semiconductor becomes a hole trap or the like. Therefore, when the silicon oxide has excess oxygen, stable electrical characteristics can be imparted to the transistor.

In addition, when one fluorine atom and one hydrogen atom enter silicon oxide, one bond is broken among four oxygen atoms bonded to one silicon atom (... Si-O-Si ...). + F + H-> ... Si--O-Si ... + F + H). Then, the fluorine atom and the silicon atom in which the bond with the oxygen atom is broken are combined (... Si--O-Si ... + F + H → ... Si-F-O-Si ... + H). Further, an oxygen atom and a hydrogen atom bonded to a silicon atom are bonded and terminated (... Si-F-O-Si ... + H → ... Si-FH-O-Si ..., FIG. 49). (See (C).)

When silicon oxide has a hydrogen trap, the hydrogen concentration of the oxide semiconductor can be reduced. Note that hydrogen in the oxide semiconductor is an impurity. For example, when hydrogen enters an oxygen deficient site in an oxide semiconductor, an electron which is a carrier may be generated. Therefore, the carrier density in the channel formation region can be reduced when silicon oxide has a hydrogen trap. As a result, the threshold voltage of the transistor can be changed in the positive direction by the amount of the reduced carrier density. In other words, the electrical characteristics of the transistor can be close to normally-off. Note that hydrogen trapped in silicon oxide has high energy required for desorption. Therefore, desorption of hydrogen trapped in silicon oxide is unlikely to occur.

Thus, generation of excess oxygen or / and hydrogen trap occurs when fluorine enters silicon oxide. Note that when excess oxygen is consumed to reduce oxygen vacancies in the oxide semiconductor, oxygen in silicon oxide is less than before fluorine enters. In addition, when hydrogen in the oxide semiconductor is trapped, the amount of hydrogen in silicon oxide is larger than that before fluorine enters.

A sufficient amount of excess oxygen and hydrogen traps may be used in order to impart stable electrical characteristics to the transistor and approach the normally-off electrical characteristics. For this purpose, for example, it is understood that the fluorine concentration of silicon oxide may be made higher than the hydrogen concentration. Note that the fluorine concentration and hydrogen concentration in silicon oxide can be compared using, for example, SIMS, Rutherford Backscattering Spectrometry (RBS), Hydrogen Forward Scattering Spectroscopy (HFS), and the like. .

<Regarding Heat Treatment> Here, a furnace control method that can be used when heat treatment is performed will be described with reference to FIG. Note that the atmosphere of the heat treatment used for description is an example, and may be changed as appropriate.

FIG. 45A illustrates an example in which the atmosphere is changed and heat treatment is performed twice. First, the workpiece is placed in the furnace. Next, nitrogen gas is put into the furnace to a first temperature. Next, the temperature is raised to the second temperature in 1 hour. Next, hold at the second temperature for 1 hour. Next, the temperature is lowered to the third temperature in 1 hour. Next, nitrogen gas and oxygen gas are put into the furnace. Next, hold at the third temperature for 1 hour. Next, the temperature is raised to the fourth temperature in 1 hour. Next, hold at the fourth temperature for 1 hour. Next, the temperature is lowered to the fifth temperature in one hour. Next, the workpiece is taken out from the furnace.

Note that the first temperature, the third temperature, and the fifth temperature are in a temperature range (for example, 50 ° C. or more and 200 ° C. or less) in which the workpiece can be taken in and out. If the first temperature, the third temperature, and the fifth temperature are too low, the time for lowering the temperature becomes long, so that the productivity may be lowered. In addition, if the first temperature and the fifth temperature are too high, the workpiece may be damaged when the workpiece is taken in or out. In addition, 2nd temperature and 4th temperature are the maximum temperature (for example, 250 to 650 degreeC) of the heat processing in each atmosphere. In this specification, when it describes as the time which heat-processed, the time hold | maintained at the maximum temperature in each atmosphere is shown.

In the method shown in FIG. 45A, it is understood that a total of 7 hours is required when heat treatment is performed for 1 hour in two kinds of atmospheres.

FIG. 45B illustrates an example in which one heat treatment is performed without switching the atmosphere. First, the workpiece is placed in the furnace. Next, ultra-dry air (CDA: Clean Dry Air) is put into the furnace to a sixth temperature. CDA is air having a water content of 20 ppm or less, 1 ppm or less, or 10 ppb or less. Next, the temperature is raised to the seventh temperature in 1 hour. Next, hold at the seventh temperature for 2 hours. Next, the temperature is lowered to the eighth temperature in one hour. Next, the workpiece is taken out from the furnace.

Note that the sixth temperature and the eighth temperature are temperature ranges in which the workpiece can be taken in and out. The seventh temperature is the maximum temperature of the heat treatment in each atmosphere.

In the method shown in FIG. 45B, it is understood that a total of 4 hours are required when heat treatment is performed for 2 hours in one kind of atmosphere.

FIG. 45C illustrates an example in which the atmosphere is changed and heat treatment is performed once. First, the workpiece is placed in the furnace. Next, nitrogen gas is put into the furnace to reach a ninth temperature. Next, the temperature is raised to the tenth temperature in one hour. Next, hold at the tenth temperature for 1 hour. Next, CDA is put into the furnace. Next, hold at the tenth temperature for 1 hour. Next, the temperature is lowered to the eleventh temperature in one hour. Next, the workpiece is taken out from the furnace.

Note that the ninth temperature and the eleventh temperature are temperature ranges in which the workpiece can be taken in and out. The tenth temperature is the maximum temperature of the heat treatment in each atmosphere.

In the method shown in FIG. 45C, it is understood that a total of 4 hours is required when the heat treatment is performed for 2 hours in two kinds of atmospheres.

Note that by performing the heat treatment with a method illustrated in FIGS. 45B and 45C, the heat treatment time can be shortened as compared with FIG. 45A. As a result, the productivity of the semiconductor device can be increased.

<Transistor 2> Next, a method for manufacturing transistors having partially different shapes will be described. 10A, 11A, 12A, 13A, 14A, 15A, and 18A illustrate a method for manufacturing a transistor. It is a top view. In each top view, an alternate long and short dash line F1-F2 and an alternate long and short dash line F3-F4 are shown, and cross-sectional views corresponding thereto are shown in FIGS. 10B, 11B, 12B, and 13B. 14 (B), FIG. 15 (B) and FIG. 18 (B).

First, the substrate 500 is prepared. For the substrate 500, the description of the substrate 400 is referred to.

Next, a conductor is formed. The conductor can be formed by sputtering, CVD, MBE, PLD, ALD, or the like.

Next, a resist or the like is formed over the conductor and processed using the resist, so that the conductor 513 is formed.

Next, an insulator is formed. The insulator can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

Next, etching is performed from the upper surface to the lower surface of the insulator so as to be in a shape parallel to the lower surface of the substrate 500, thereby exposing the conductor 513 and forming the insulator 503 (FIG. 10A). And FIG. 10B). By forming the insulator 503 by such a method, the height of the upper surface of the conductor 513 and the height of the upper surface of the insulator 503 can be made comparable. Therefore, it is possible to suppress a shape defect in a later process.

Next, the insulator 502 is formed (see FIGS. 11A and 11B). The insulator 502 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. For the insulator 502, the description of the insulator 402 is referred to.

Next, a semiconductor 536a is formed. The semiconductor 536a can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. For the semiconductor 536a, the description of the semiconductor to be the semiconductor 406a is referred to.

Next, a semiconductor 536b is formed. The semiconductor 536b can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. For the semiconductor 536b, the description of the semiconductor to be the semiconductor 406b is referred to. Note that the semiconductor film 536a and the semiconductor film 536b are formed in succession without being exposed to the air, whereby entry of impurities into the film and the interface can be reduced.

Next, it is preferable to perform a heat treatment. The heat treatment may be performed at 250 ° C to 650 ° C, preferably 450 ° C to 600 ° C, more preferably 520 ° C to 570 ° C. The heat treatment is performed in an inert gas atmosphere or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. The heat treatment may be performed in a reduced pressure state. Alternatively, the heat treatment may be performed in an atmosphere containing an oxidizing gas of 10 ppm or more, 1% or more, or 10% or more in order to supplement the desorbed oxygen after the heat treatment in an inert gas atmosphere. By the heat treatment, the crystallinity of the semiconductor 536a and the semiconductor 536b can be increased, impurities such as hydrogen and water can be removed, and the like. For the heat treatment, an RTA apparatus using lamp heating can be used. In the case where a CAAC-OS is used for the semiconductor 536a and the semiconductor 536b, the peak intensity is increased and the full width at half maximum is decreased by performing heat treatment. That is, the crystallinity of the CAAC-OS is increased by heat treatment. The heat treatment by the RTA apparatus is effective for improving productivity because it takes a shorter time than a furnace. In this manner, by increasing the temperature and time of heat treatment, the CAAC-OS can have higher density and can be made closer to the physical properties of a single crystal.

Next, a conductor is formed. The conductor can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. For the conductor, the description of the conductor to be the conductor 416a and the conductor 416b is referred to.

Next, a resist or the like is formed over the conductor and processed using the resist, so that the conductor 516a and the conductor 516b are formed (see FIGS. 12A and 12B).

Next, a resist or the like is formed over the semiconductor 536b and processed using the resist, the conductor 516a, and the conductor 516b, so that the semiconductor 506b and the semiconductor 506a are formed (see FIGS. 13A and 13B). .)

Note that the conductor 516a, the conductor 516b, the semiconductor 506a, and the semiconductor 506b may be formed by the following method after the conductor is formed.

First, a resist or the like is formed over the conductor and processed using the resist to form the conductor 516, the semiconductor 506b, and the semiconductor 506a (see FIGS. 16A and 16B). At this time, the semiconductor 506b and the semiconductor 506a may be processed using the conductor 516 after the resist is removed.

Next, a resist or the like is formed over the conductor 516 and processed using the resist, so that the conductor 516a and the conductor 516b are formed (see FIGS. 13A and 13B).

Next, a semiconductor 536c is formed. The semiconductor 536c can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. For the semiconductor 536c, the description of the semiconductor 436c is referred to.

Next, the insulator 542 is formed. The insulator 542 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. For the insulator 542, the description of the insulator 442 is referred to.

Next, a conductor 534 is formed (see FIGS. 14A and 14B). The conductor 534 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. For the conductor 534, the description of the conductor 434 is referred to.

Next, a resist or the like is formed over the conductor 534 and processed using the resist, so that the conductor 504 is formed. Further, the insulator 542 is processed using the resist or the conductor 504, so that the insulator 512 is formed. Further, the semiconductor 536c is processed using the resist, the conductor 504, or the insulator 542, so that the semiconductor 506c is formed (see FIGS. 15A and 15B). Note that here, the semiconductor 506c, the insulator 512, and the conductor 504 are processed so as to have the same shape when viewed from above, but the shape is not limited thereto. For example, the insulator 512 and the conductor 504 may be processed using different resists. For example, after forming the insulator 512, a conductor to be the conductor 504 may be formed, or after forming the conductor 504, a resist or the like is separately formed over the insulator to be the insulator 512. May be. For example, the semiconductor 506c may be connected to an adjacent transistor or the like.

Next, an insulator may be formed. The insulator can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

As the insulator, for example, an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium or tantalum, A single layer or a stacked layer may be used. As the insulator, an insulator containing aluminum oxide, silicon nitride oxide, silicon nitride, gallium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide or tantalum oxide is preferably used in a single layer or a stacked layer. That's fine.

The insulator preferably has a function as a barrier layer. The insulator has a function of blocking oxygen or / and hydrogen, for example. Alternatively, the insulator preferably has a higher ability to block oxygen and / or hydrogen than the insulator 502 or the insulator 512, for example.

Next, excess oxygen may be included in the insulator by adding oxygen ions while heating the substrate.

Through the above steps, the transistor according to one embodiment of the present invention can be manufactured.

In the transistor illustrated in FIG. 15B, the insulator 502 and / or the insulator 512 or the like includes excess oxygen. Through these actions, oxygen vacancies or hydrogen in the semiconductor 506a, the semiconductor 506b, and the semiconductor 506c can be reduced. That is, a transistor having excellent electrical characteristics can be provided.

As shown in FIG. 15B, the transistor has an s-channel structure. Further, an electric field from the conductor 504 and the conductor 513 is unlikely to be inhibited by the conductor 516a and the conductor 516b on the side surface of the semiconductor 506b.

Note that the conductor 513 is not necessarily formed (see FIG. 17A). Alternatively, the insulator 512 and the semiconductor 506c may protrude from the conductor 504 (see FIG. 17B). Further, the insulator 542 and the semiconductor 536c are not necessarily processed (see FIG. 17C). Further, the width of the conductor 513 in the F1-F2 cross section may be larger than that of the semiconductor 506b (see FIG. 18A). The conductor 513 and the conductor 504 may be in contact with each other through an opening (see FIG. 18B). The conductor 504 is not necessarily provided (see FIG. 18C). .

<Circuit> An example of a circuit of a semiconductor device using a transistor or the like according to one embodiment of the present invention will be described below.

<CMOS Inverter> The circuit diagram shown in FIG. 19A shows a structure of a so-called CMOS inverter in which a p-channel transistor 2200 and an n-channel transistor 2100 are connected in series and their gates are connected. Yes.

<Structure 1 of Semiconductor Device> FIG. 20 is a cross-sectional view of a semiconductor device corresponding to FIG. The semiconductor device illustrated in FIG. 20 includes a transistor 2200 and a transistor 2100. The transistor 2100 is provided above the transistor 2200. Note that although the example in which the transistor illustrated in FIGS. 15A and 15B is used as the transistor 2100 is described, the semiconductor device according to one embodiment of the present invention is not limited thereto. For example, the transistor illustrated in FIGS. 6, 7, 8, 17, 18, or the like may be used as the transistor 2100. Therefore, for the transistor 2100, the above description of the transistor is referred to as appropriate.

A transistor 2200 illustrated in FIG. 20 is a transistor including a semiconductor substrate 450. The transistor 2200 includes a region 472a in the semiconductor substrate 450, a region 472b in the semiconductor substrate 450, an insulator 462, and a conductor 454.

In the transistor 2200, the region 472a and the region 472b function as a source region and a drain region. The insulator 462 functions as a gate insulator. The conductor 454 functions as a gate electrode. Therefore, the resistance of the channel formation region can be controlled by the potential applied to the conductor 454. That is, conduction / non-conduction between the region 472a and the region 472b can be controlled by a potential applied to the conductor 454.

As the semiconductor substrate 450, for example, a single semiconductor substrate such as silicon or germanium, or a semiconductor substrate such as silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide may be used. A single crystal silicon substrate is preferably used as the semiconductor substrate 450.

As the semiconductor substrate 450, a semiconductor substrate having an impurity imparting n-type conductivity is used. However, as the semiconductor substrate 450, a semiconductor substrate having an impurity imparting p-type conductivity may be used. In that case, a well having an impurity imparting n-type conductivity may be provided in a region to be the transistor 2200. Alternatively, the semiconductor substrate 450 may be i-type.

The upper surface of the semiconductor substrate 450 preferably has a (110) plane. Thus, the on-state characteristics of the transistor 2200 can be improved.

The region 472a and the region 472b are regions having an impurity imparting p-type conductivity. In this manner, the transistor 2200 constitutes a p-channel transistor.

Note that the transistor 2200 is separated from an adjacent transistor by the region 460 or the like. The region 460 is a region having an insulating property.

20 includes an insulator 464, an insulator 466, an insulator 468, a conductor 480a, a conductor 480b, a conductor 480c, a conductor 478a, a conductor 478b, and a conductor. 478c, a conductor 476a, a conductor 476b, a conductor 474a, a conductor 474b, a conductor 474c, a conductor 496a, a conductor 496b, a conductor 496c, a conductor 496d, and a conductor 498a, a conductor 498b, a conductor 498c, an insulator 490, an insulator 492, and an insulator 494 are included.

The insulator 464 is provided over the transistor 2200. The insulator 466 is provided over the insulator 464. The insulator 468 is provided over the insulator 466. The insulator 490 is provided over the insulator 468. The transistor 2100 is provided over the insulator 490. The insulator 492 is provided over the transistor 2100. The insulator 494 is provided over the insulator 492.

The insulator 464 includes an opening reaching the region 472a, an opening reaching the region 472b, and an opening reaching the conductor 454. In addition, a conductor 480a, a conductor 480b, or a conductor 480c is embedded in each opening.

The insulator 466 includes an opening reaching the conductor 480a, an opening reaching the conductor 480b, and an opening reaching the conductor 480c. In addition, a conductor 478a, a conductor 478b, or a conductor 478c is embedded in each opening.

The insulator 468 includes an opening reaching the conductor 478b and an opening reaching the conductor 478c. In addition, a conductor 476a or a conductor 476b is embedded in each opening.

The insulator 490 includes an opening overlapping with a channel formation region of the transistor 2100, an opening reaching the conductor 476a, and an opening reaching the conductor 476b. In addition, a conductor 474a, a conductor 474b, or a conductor 474c is embedded in each opening.

The conductor 474a may function as the gate electrode of the transistor 2100. Alternatively, for example, electrical characteristics such as a threshold voltage of the transistor 2100 may be controlled by applying a certain potential to the conductor 474a. Alternatively, for example, the conductor 474a and the conductor 404 functioning as a gate electrode of the transistor 2100 may be electrically connected. Thus, the on-state current of the transistor 2100 can be increased. In addition, since the punch-through phenomenon can be suppressed, electrical characteristics in the saturation region of the transistor 2100 can be stabilized.

The insulator 492 includes an opening reaching the conductor 474b through the conductor 516b which is one of the source electrode and the drain electrode of the transistor 2100 and the conductor 516a which is the other of the source electrode and the drain electrode of the transistor 2100. , An opening reaching the conductor 504 which is a gate electrode of the transistor 2100, and an opening reaching the conductor 474c. In addition, a conductor 496a, a conductor 496b, a conductor 496c, or a conductor 496d is embedded in each opening. Note that each opening may be provided through an opening further included in any of the components such as the transistor 2100.

The insulator 494 includes an opening reaching the conductor 496a, an opening reaching the conductor 496b and the conductor 496d, and an opening reaching the conductor 496c. In addition, a conductor 498a, a conductor 498b, or a conductor 498c is embedded in each opening.

As the insulator 464, the insulator 466, the insulator 468, the insulator 490, the insulator 492, and the insulator 494, for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, An insulator containing gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum may be used as a single layer or a stacked layer. For example, as the insulator 401, aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or oxide Tantalum may be used.

One or more of the insulator 464, the insulator 466, the insulator 468, the insulator 490, the insulator 492, or the insulator 494 preferably includes an insulator having a function of blocking impurities such as hydrogen and oxygen. When an insulator having a function of blocking impurities such as hydrogen and oxygen is provided in the vicinity of the transistor 2100, the electrical characteristics of the transistor 2100 can be stabilized.

Examples of the insulator having a function of blocking impurities such as hydrogen and oxygen include boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, and lanthanum. An insulator containing neodymium, hafnium, or tantalum may be used as a single layer or a stacked layer.

Conductor 480a, conductor 480b, conductor 480c, conductor 478a, conductor 478b, conductor 478c, conductor 476a, conductor 476b, conductor 474a, conductor 474b, conductor 474c, conductor 496a, conductor 496b, conductor 496c, conductor 496d, conductor 498a, conductor 498b, and conductor 498c include, for example, boron, nitrogen, oxygen, fluorine, silicon, phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel, A conductor including one or more of copper, zinc, gallium, yttrium, zirconium, molybdenum, ruthenium, silver, indium, tin, tantalum, and tungsten may be used in a single layer or a stacked layer. For example, it may be an alloy or a compound, a conductor containing aluminum, a conductor containing copper and titanium, a conductor containing copper and manganese, a conductor containing indium, tin and oxygen, a conductor containing titanium and nitrogen Etc. may be used.

Note that the semiconductor device illustrated in FIG. 21 is different only in the structure of the transistor 2200 of the semiconductor device illustrated in FIG. Therefore, for the semiconductor device illustrated in FIG. 21, the description of the semiconductor device illustrated in FIG. Specifically, the semiconductor device illustrated in FIG. 21 illustrates the case where the transistor 2200 is a Fin type. By setting the transistor 2200 to be a Fin type, an effective channel width can be increased, whereby the on-state characteristics of the transistor 2200 can be improved. In addition, since the contribution of the electric field of the gate electrode can be increased, off characteristics of the transistor 2200 can be improved.

Further, the semiconductor device illustrated in FIG. 22 is different only in the structure of the transistor 2200 of the semiconductor device illustrated in FIG. Therefore, the description of the semiconductor device illustrated in FIG. 20 is referred to for the semiconductor device illustrated in FIG. Specifically, the semiconductor device illustrated in FIG. 22 illustrates the case where the transistor 2200 is provided over a semiconductor substrate 450 which is an SOI substrate. FIG. 22 illustrates a structure in which the region 456 is separated from the semiconductor substrate 450 by an insulator 452. By using an SOI substrate as the semiconductor substrate 450, a punch-through phenomenon or the like can be suppressed, so that off characteristics of the transistor 2200 can be improved. Note that the insulator 452 can be formed by making the semiconductor substrate 450 an insulator. For example, as the insulator 452, silicon oxide can be used.

In the semiconductor device illustrated in FIGS. 20 to 22, a p-channel transistor is manufactured using a semiconductor substrate and an n-channel transistor is formed thereabove, so that the area occupied by the element can be reduced. That is, the degree of integration of the semiconductor device can be increased. Further, since the process can be simplified as compared with the case where an n-channel transistor and a p-channel transistor are formed using the same semiconductor substrate, the productivity of the semiconductor device can be increased. In addition, the yield of the semiconductor device can be increased. In some cases, a p-channel transistor can omit complicated processes such as an LDD (Lightly Doped Drain) region, a shallow trench structure, and strain design. Therefore, productivity and yield may be increased as compared with the case where an n-channel transistor is manufactured using a semiconductor substrate.

<CMOS Analog Switch> The circuit diagram shown in FIG. 19B shows a structure in which the sources and drains of the transistors 2100 and 2200 are connected. With such a configuration, it can function as a so-called CMOS analog switch.

<Storage device 1> An example of a semiconductor device (storage device) that uses a transistor according to one embodiment of the present invention and can store stored data even when power is not supplied and has no limit on the number of times of writing. 23.

A semiconductor device illustrated in FIG. 23A includes a transistor 3200 including a first semiconductor, a transistor 3300 including a second semiconductor, and a capacitor 3400. Note that the above-described transistor can be used as the transistor 3300.

The transistor 3300 is preferably a transistor with low off-state current. As the transistor 3300, for example, a transistor including an oxide semiconductor can be used. Since the off-state current of the transistor 3300 is small, stored data can be held in a specific node of the semiconductor device for a long time. That is, a refresh operation is not required or the frequency of the refresh operation can be extremely low, so that the semiconductor device with low power consumption is obtained.

In FIG. 23A, the first wiring 3001 is electrically connected to the source of the transistor 3200, and the second wiring 3002 is electrically connected to the drain of the transistor 3200. The third wiring 3003 is electrically connected to one of a source and a drain of the transistor 3300, and the fourth wiring 3004 is electrically connected to the gate of the transistor 3300. The gate of the transistor 3200 and the other of the source and the drain of the transistor 3300 are electrically connected to one of the electrodes of the capacitor 3400, and the fifth wiring 3005 is electrically connected to the other of the electrodes of the capacitor 3400. Has been.

The semiconductor device illustrated in FIG. 23A has a characteristic that the potential of the gate of the transistor 3200 can be held; thus, information can be written, held, and read as described below.

Information writing and holding will be described. First, the potential of the fourth wiring 3004 is set to a potential at which the transistor 3300 is turned on, so that the transistor 3300 is turned on. Accordingly, the potential of the third wiring 3003 is supplied to the node FG electrically connected to one of the gate of the transistor 3200 and the electrode of the capacitor 3400. That is, predetermined charge is supplied to the gate of the transistor 3200 (writing). Here, it is assumed that one of two charges that give two different potential levels (hereinafter referred to as a Low level charge and a High level charge) is given. After that, the potential of the fourth wiring 3004 is set to a potential at which the transistor 3300 is turned off and the transistor 3300 is turned off, so that charge is held at the node FG (holding).

Since the off-state current of the transistor 3300 is small, the charge of the node FG is held for a long time.

Next, reading of information will be described. When an appropriate potential (reading potential) is applied to the fifth wiring 3005 in a state where a predetermined potential (constant potential) is applied to the first wiring 3001, the second wiring 3002 has a charge held in the node FG. Take a potential according to the amount. This is because, when the transistor 3200 is an n-channel type, the apparent threshold voltage V _{th_H} when a high level charge is applied to the gate of the transistor 3200 is the low level charge applied to the gate of the transistor 3200. This is because it becomes lower than the apparent threshold voltage V _{th_L in the} case of being present. Here, the apparent threshold voltage refers to the potential of the fifth wiring 3005 necessary for bringing the transistor 3200 into a “conducting state”. Therefore, by _setting the potential of the fifth wiring 3005 to a potential V ₀ between V _{th_H} and V _{th_L} , the charge given to the node FG can be determined. For example, in the case where a high-level charge is applied to the node FG in writing, the transistor 3200 is in a “conducting state” if the potential of the fifth wiring 3005 is V ₀ (> V _{th_H} ). On the other hand, when a low-level charge is _{supplied to} the node FG, the transistor 3200 remains in the “non-conductive state” even when the potential of the fifth wiring 3005 becomes V ₀ (<V _{th_L} ). Therefore, by determining the potential of the second wiring 3002, information held in the node FG can be read.

Note that when memory cells are arranged in an array, information of a desired memory cell must be read at the time of reading. In order not to read data in other memory cells, the fifth wiring 3005 is _{supplied with} a potential at which the transistor 3200 is in a “non-conducting state” regardless of the charge applied to the node FG, that is, a potential lower than V _{th_H.} To give. _{Alternatively} , the fifth wiring 3005 may be _{supplied with} a potential at which the transistor 3200 is in a “conducting state” regardless of the charge applied to the node FG, that is, a potential higher than V _{th_L} .

<Structure 2 of Semiconductor Device> FIG. 24 is a cross-sectional view of the semiconductor device corresponding to FIG. The semiconductor device illustrated in FIG. 24 includes a transistor 3200, a transistor 3300, and a capacitor 3400. The transistor 3300 and the capacitor 3400 are provided above the transistor 3200. Note that as the transistor 3300, the above description of the transistor 2100 is referred to. For the transistor 3200, the description of the transistor 2200 illustrated in FIGS. Note that although FIG. 20 illustrates the case where the transistor 2200 is a p-channel transistor, the transistor 3200 may be an n-channel transistor.

A transistor 2200 illustrated in FIG. 24 is a transistor including a semiconductor substrate 450. The transistor 2200 includes a region 472a in the semiconductor substrate 450, a region 472b in the semiconductor substrate 450, an insulator 462, and a conductor 454.

24 includes an insulator 464, an insulator 466, an insulator 468, a conductor 480a, a conductor 480b, a conductor 480c, a conductor 478a, a conductor 478b, and a conductor. 478c, a conductor 476a, a conductor 476b, a conductor 474a, a conductor 474b, a conductor 474c, a conductor 496a, a conductor 496b, a conductor 496c, a conductor 496d, and a conductor 498a, a conductor 498b, a conductor 498c, a conductor 498d, an insulator 490, an insulator 492, and an insulator 494 are provided.

The insulator 464 is provided over the transistor 3200. The insulator 466 is provided over the insulator 464. The insulator 468 is provided over the insulator 466. The insulator 490 is provided over the insulator 468. The transistor 2100 is provided over the insulator 490. The insulator 492 is provided over the transistor 2100. The insulator 494 is provided over the insulator 492.

The insulator 464 includes an opening reaching the region 472a, an opening reaching the region 472b, and an opening reaching the conductor 454. In addition, a conductor 480a, a conductor 480b, or a conductor 480c is embedded in each opening.

The insulator 466 includes an opening reaching the conductor 480a, an opening reaching the conductor 480b, and an opening reaching the conductor 480c. In addition, a conductor 478a, a conductor 478b, or a conductor 478c is embedded in each opening.

The insulator 468 includes an opening reaching the conductor 478b and an opening reaching the conductor 478c. In addition, a conductor 476a or a conductor 476b is embedded in each opening.

The insulator 490 includes an opening overlapping with a channel formation region of the transistor 3300, an opening reaching the conductor 476a, and an opening reaching the conductor 476b. In addition, a conductor 474a, a conductor 474b, or a conductor 474c is embedded in each opening.

The conductor 474a may function as the bottom gate electrode of the transistor 3300. Alternatively, for example, electrical characteristics such as a threshold voltage of the transistor 3300 may be controlled by applying a certain potential to the conductor 474a. Alternatively, for example, the conductor 474a and the conductor 404 that is the top gate electrode of the transistor 3300 may be electrically connected. Thus, the on-state current of the transistor 3300 can be increased. In addition, since the punch-through phenomenon can be suppressed, electrical characteristics in the saturation region of the transistor 3300 can be stabilized.

The insulator 492 includes an opening reaching the conductor 474b through the conductor 516b which is one of the source electrode and the drain electrode of the transistor 3300 and the conductor 516a which is the other of the source electrode and the drain electrode of the transistor 3300. Through the insulator 512, the opening reaching the conductor 514, the opening reaching the conductor 504 which is the gate electrode of the transistor 3300, and the conductor 516a which is the other of the source electrode and the drain electrode of the transistor 3300. And an opening reaching the conductor 474c. In addition, a conductor 496a, a conductor 496b, a conductor 496c, or a conductor 496d is embedded in each opening. Note that each opening may further pass through an opening included in any of the components such as the transistor 3300.

The insulator 494 includes an opening reaching the conductor 496a, an opening reaching the conductor 496b, an opening reaching the conductor 496c, and an opening reaching the conductor 496d. In addition, a conductor 498a, a conductor 498b, a conductor 498c, or a conductor 498d is embedded in each opening.

One or more of the insulator 464, the insulator 466, the insulator 468, the insulator 490, the insulator 492, or the insulator 494 preferably includes an insulator having a function of blocking impurities such as hydrogen and oxygen. When an insulator having a function of blocking impurities such as hydrogen and oxygen is provided in the vicinity of the transistor 3300, electrical characteristics of the transistor 3300 can be stabilized.

Examples of the conductor 498d include boron, nitrogen, oxygen, fluorine, silicon, phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel, copper, zinc, gallium, yttrium, zirconium, molybdenum, ruthenium, silver, indium, A conductor containing one or more of tin, tantalum, and tungsten may be used in a single layer or a stacked layer. For example, it may be an alloy or a compound, a conductor containing aluminum, a conductor containing copper and titanium, a conductor containing copper and manganese, a conductor containing indium, tin and oxygen, a conductor containing titanium and nitrogen Etc. may be used.

The source or the drain of the transistor 3200 is one of a source electrode and a drain electrode of the transistor 3300 through the conductor 480 b , the conductor 478 b , the conductor 476 a, the conductor 474 b , and the conductor 496 c. It is electrically connected to the conductor 516b. The conductor 454 which is a gate electrode of the transistor 3200 includes a conductor 480c, a conductor 478c, a conductor 476b, a conductor 474c, and a conductor 496d, and the source or drain electrode of the transistor 3300. It is electrically connected to a conductor 516a which is the other of the above.

The capacitor 3400 includes an electrode electrically connected to the other of the source electrode and the drain electrode of the transistor 3300, a conductor 514, and an insulator 511. Note that since the insulator 511 can be formed through the same process as the insulator 512 functioning as a gate insulator of the transistor 3300, productivity may be increased, which may be preferable. In addition, when the layer formed through the same step as the conductor 504 functioning as the gate electrode of the transistor 3300 is used as the conductor 514, productivity may be increased, which may be preferable.

For other structures, the description of FIG. 20 and the like can be referred to as appropriate.

Note that the semiconductor device illustrated in FIG. 25 is different only in the structure of the transistor 3200 of the semiconductor device illustrated in FIG. Therefore, the description of the semiconductor device illustrated in FIG. 24 is referred to for the semiconductor device illustrated in FIG. Specifically, the semiconductor device illustrated in FIG. 25 illustrates the case where the transistor 3200 is a Fin type. For the Fin-type transistor 3200, the description of the transistor 2200 illustrated in FIGS. Note that although FIG. 21 illustrates the case where the transistor 2200 is a p-channel transistor, the transistor 3200 may be an n-channel transistor.

The semiconductor device shown in FIG. 26 is different only in the structure of the transistor 3200 of the semiconductor device shown in FIG. Therefore, the description of the semiconductor device illustrated in FIG. 24 is referred to for the semiconductor device illustrated in FIG. Specifically, the semiconductor device illustrated in FIG. 26 illustrates the case where the transistor 3200 is provided over a semiconductor substrate 450 which is an SOI substrate. For the transistor 3200 provided over the semiconductor substrate 450 which is an SOI substrate, the description of the transistor 2200 illustrated in FIGS. Note that although FIG. 22 illustrates the case where the transistor 2200 is a p-channel transistor, the transistor 3200 may be an n-channel transistor.

<Storage Device 2> The semiconductor device shown in FIG. 23B is different from the semiconductor device shown in FIG. 23A in that the transistor 3200 is not provided. In this case also, data can be written and held by the same operation as that of the semiconductor device shown in FIG.

Information reading in the semiconductor device illustrated in FIG. 23B is described. When the transistor 3300 is turned on, the floating third wiring 3003 and the capacitor 3400 are turned on, and charge is redistributed between the third wiring 3003 and the capacitor 3400. As a result, the potential of the third wiring 3003 changes. The amount of change in potential of the third wiring 3003 varies depending on one potential of the electrode of the capacitor 3400 (or charge accumulated in the capacitor 3400).

For example, the potential of one electrode of the capacitor 3400 is V, the capacitance of the capacitor 3400 is C, the capacitance component of the third wiring 3003 is CB, and the potential of the third wiring 3003 before the charge is redistributed. Assuming VB0, the potential of the third wiring 3003 after the charge is redistributed is (CB × VB0 + CV) / (CB + C). Therefore, if the potential of one of the electrodes of the capacitor 3400 assumes two states of V1 and V0 (V1> V0) as the state of the memory cell, the third wiring 3003 in the case where the potential V1 is held. It can be seen that the potential (= (CB × VB0 + CV1) / (CB + C)) is higher than the potential of the third wiring 3003 when the potential V0 is held (= (CB × VB0 + CV0) / (CB + C)). .

Then, information can be read by comparing the potential of the third wiring 3003 with a predetermined potential.

In this case, a transistor to which the first semiconductor is applied is used as a driver circuit for driving the memory cell, and a transistor to which the second semiconductor is applied is stacked over the driver circuit as the transistor 3300. do it.

The semiconductor device described above can hold stored data for a long time by using a transistor with an off-state current that includes an oxide semiconductor. That is, a refresh operation is unnecessary or the frequency of the refresh operation can be extremely low, so that a semiconductor device with low power consumption can be realized. In addition, stored data can be held for a long time even when power is not supplied (note that a potential is preferably fixed).

In addition, since the semiconductor device does not require a high voltage for writing information, the element hardly deteriorates. For example, unlike the conventional nonvolatile memory, since electrons are not injected into the floating gate and electrons are not extracted from the floating gate, there is no problem of deterioration of the insulator. In other words, the semiconductor device according to one embodiment of the present invention is a semiconductor device in which the number of rewritable times which is a problem in the conventional nonvolatile memory is not limited and the reliability is drastically improved. Further, since data is written depending on the conductive state and non-conductive state of the transistor, high-speed operation is possible.

<Imaging Device> An imaging device according to one embodiment of the present invention will be described below.

FIG. 27A is a plan view illustrating an example of an imaging device 200 according to one embodiment of the present invention. The imaging device 200 includes a pixel unit 210, a peripheral circuit 260 for driving the pixel unit 210, a peripheral circuit 270, a peripheral circuit 280, and a peripheral circuit 290. The pixel unit 210 includes a plurality of pixels 211 arranged in a matrix of p rows and q columns (p and q are integers of 2 or more). The peripheral circuit 260, the peripheral circuit 270, the peripheral circuit 280, and the peripheral circuit 290 are connected to the plurality of pixels 211 and have a function of supplying signals for driving the plurality of pixels 211, respectively. Note that in this specification and the like, the peripheral circuit 260, the peripheral circuit 270, the peripheral circuit 280, the peripheral circuit 290, and the like are all referred to as “peripheral circuits” or “driving circuits” in some cases. For example, the peripheral circuit 260 can be said to be part of the peripheral circuit.

The imaging apparatus 200 preferably includes a light source 291. The light source 291 can emit the detection light P1.

The peripheral circuit includes at least one of a logic circuit, a switch, a buffer, an amplifier circuit, and a conversion circuit. In addition, the peripheral circuit may be disposed on a substrate over which the pixel portion 210 is formed. The peripheral circuit may be partially or entirely mounted with a semiconductor device such as an IC. Note that one or more of the peripheral circuit 260, the peripheral circuit 270, the peripheral circuit 280, and the peripheral circuit 290 may be omitted from the peripheral circuit.

In addition, as illustrated in FIG. 27B, in the pixel portion 210 included in the imaging device 200, the pixel 211 may be inclined. By arranging the pixels 211 at an angle, the pixel interval (pitch) in the row direction and the column direction can be shortened. Thereby, the quality of imaging in the imaging apparatus 200 can be further improved.

<Pixel Configuration Example 1> A single pixel 211 included in the imaging apparatus 200 includes a plurality of subpixels 212, and each subpixel 212 is combined with a filter (color filter) that transmits light in a specific wavelength band. Information for realizing color image display can be acquired.

FIG. 28A is a plan view illustrating an example of a pixel 211 for acquiring a color image. A pixel 211 illustrated in FIG. 28A has a sub-pixel 212 (hereinafter also referred to as “sub-pixel 212R”) provided with a color filter that transmits a red (R) wavelength band, and a green (G) wavelength band. Sub-pixel 212 (hereinafter also referred to as “sub-pixel 212G”) provided with a transparent color filter and sub-pixel 212 (hereinafter referred to as “sub-pixel 212B”) provided with a color filter that transmits the blue (B) wavelength band. Also called). The sub-pixel 212 can function as a photosensor.

The subpixel 212 (subpixel 212R, subpixel 212G, and subpixel 212B) is electrically connected to the wiring 231, the wiring 247, the wiring 248, the wiring 249, and the wiring 250. Further, the sub-pixel 212R, the sub-pixel 212G, and the sub-pixel 212B are each connected to an independent wiring 253. In this specification and the like, for example, the wiring 248 and the wiring 249 connected to the pixel 211 in the n-th row are referred to as a wiring 248 [n] and a wiring 249 [n], respectively. For example, the wiring 253 connected to the pixel 211 in the m-th column is referred to as a wiring 253 [m]. In FIG. 28A, the wiring 253 connected to the subpixel 212R included in the pixel 211 in the m-th column is the wiring 253 [m] R, the wiring 253 connected to the subpixel 212G is the wiring 253 [m] G, and A wiring 253 connected to the subpixel 212B is described as a wiring 253 [m] B. The subpixel 212 is electrically connected to a peripheral circuit through the wiring.

In addition, the imaging apparatus 200 has a configuration in which subpixels 212 provided with color filters that transmit the same wavelength band of adjacent pixels 211 are electrically connected to each other via a switch. In FIG. 28B, the sub-pixel 212 included in the pixel 211 arranged in n rows (n is an integer of 1 to p) and m columns (m is an integer of 1 to q) is adjacent to the pixel 211. A connection example of the sub-pixel 212 included in the pixel 211 arranged in n + 1 rows and m columns is shown. In FIG. 28B, a subpixel 212R arranged in n rows and m columns and a subpixel 212R arranged in n + 1 rows and m columns are connected via a switch 201. Further, the sub-pixel 212G arranged in n rows and m columns and the sub-pixel 212G arranged in n + 1 rows and m columns are connected via a switch 202. Further, the sub-pixel 212B arranged in n rows and m columns and the sub-pixel 212B arranged in n + 1 rows and m columns are connected via a switch 203.

Note that the color filter used for the sub-pixel 212 is not limited to red (R), green (G), and blue (B), and transmits cyan (C), yellow (Y), and magenta (M) light, respectively. A color filter may be used. A full color image can be acquired by providing the sub-pixel 212 that detects light of three different wavelength bands in one pixel 211.

Alternatively, in addition to the sub-pixel 212 provided with a color filter that transmits red (R), green (G), and blue (B) light, a color filter that transmits yellow (Y) light is provided. A pixel 211 having a sub-pixel 212 may be used. Alternatively, in addition to the sub-pixel 212 provided with a color filter that transmits cyan (C), yellow (Y), and magenta (M) light, a color filter that transmits blue (B) light is provided. A pixel 211 having a sub-pixel 212 may be used. By providing the sub-pixel 212 that detects light of four different wavelength bands in one pixel 211, the color reproducibility of the acquired image can be further enhanced.

Also, for example, in FIG. 28A, the pixel number ratio of the sub-pixel 212 that detects the red wavelength band, the sub-pixel 212 that detects the green wavelength band, and the sub-pixel 212 that detects the blue wavelength band (or (Light receiving area ratio) may not be 1: 1: 1. For example, a Bayer array in which the pixel number ratio (light receiving area ratio) is red: green: blue = 1: 2: 1 may be used. Alternatively, the pixel number ratio (light receiving area ratio) may be red: green: blue = 1: 6: 1.

Note that the number of subpixels 212 provided in the pixel 211 may be one, but two or more are preferable. For example, by providing two or more sub-pixels 212 that detect the same wavelength band, redundancy can be increased and the reliability of the imaging apparatus 200 can be increased.

In addition, by using an IR (IR: Infrared) filter that absorbs or reflects visible light and transmits infrared light, the imaging device 200 that detects infrared light can be realized.

Further, by using an ND (ND: Neutral Density) filter (a neutral density filter), it is possible to prevent output saturation that occurs when a large amount of light enters the photoelectric conversion element (light receiving element). By using a combination of ND filters having different light reduction amounts, the dynamic range of the imaging apparatus can be increased.

In addition to the filters described above, a lens may be provided in the pixel 211. Here, an arrangement example of the pixel 211, the filter 254, and the lens 255 will be described with reference to a cross-sectional view of FIG. By providing the lens 255, the photoelectric conversion element can receive incident light efficiently. Specifically, as illustrated in FIG. 29A, the light 256 is supplied to the photoelectric conversion element 220 through the lens 255, the filter 254 (filter 254R, the filter 254G, and the filter 254B) formed in the pixel 211, the pixel circuit 230, and the like. It can be set as the structure made to enter.

However, as illustrated in the region surrounded by the alternate long and short dash line, part of the light 256 indicated by the arrow may be blocked by part of the wiring 257. Therefore, a structure in which a lens 255 and a filter 254 are disposed on the photoelectric conversion element 220 side as illustrated in FIG. 29B so that the photoelectric conversion element 220 receives light 256 efficiently is preferable. By making the light 256 incident on the photoelectric conversion element 220 from the photoelectric conversion element 220 side, the imaging device 200 with high detection sensitivity can be provided.

As the photoelectric conversion element 220 illustrated in FIG. 29, a photoelectric conversion element in which a pn-type junction or a pin-type junction is formed may be used.

Alternatively, the photoelectric conversion element 220 may be formed using a substance having a function of generating charges by absorbing radiation. Examples of the substance having a function of absorbing radiation and generating a charge include selenium, lead iodide, mercury iodide, gallium arsenide, cadmium telluride, and cadmium zinc alloy.

For example, when selenium is used for the photoelectric conversion element 220, the photoelectric conversion element 220 having a light absorption coefficient over a wide wavelength band such as X-rays and gamma rays in addition to visible light, ultraviolet light, and infrared light can be realized.

Here, one pixel 211 included in the imaging apparatus 200 may include a sub-pixel 212 including a first filter in addition to the sub-pixel 212 illustrated in FIG.

<Pixel Configuration Example 2> An example in which a pixel is configured using a transistor using silicon and a transistor using an oxide semiconductor will be described below.

30A and 30B are cross-sectional views of elements included in the imaging device. An imaging device illustrated in FIG. 30A includes a transistor 351 using silicon provided over a silicon substrate 300, a transistor 352 and a transistor 353 using an oxide semiconductor stacked over the transistor 351, and a silicon substrate. 300 includes a photodiode 360 provided. Each transistor and photodiode 360 has electrical connection with various plugs 370 and wirings 371. Further, the anode 361 of the photodiode 360 is electrically connected to the plug 370 through the low resistance region 363.

The imaging device is provided in contact with the layer 310 including the transistor 351 and the photodiode 360 provided over the silicon substrate 300, the layer 320 including the wiring 371, and the layer 320 including the wiring 371. A layer 330 including the transistor 353, and a layer 340 provided in contact with the layer 330 and including a wiring 372 and a wiring 373.

Note that in the example of the cross-sectional view in FIG. 30A, the silicon substrate 300 has a light-receiving surface of the photodiode 360 on a surface opposite to a surface where the transistor 351 is formed. With this configuration, an optical path can be secured without being affected by various transistors and wirings. Therefore, a pixel with a high aperture ratio can be formed. Note that the light receiving surface of the photodiode 360 may be the same as the surface on which the transistor 351 is formed.

Note that in the case where a pixel is formed using a transistor, the layer 310 may be a layer including a transistor. Alternatively, the layer 310 may be omitted, and the pixel may be formed using only transistors.

Note that in the case where a pixel is formed using a transistor, the layer 330 may be omitted. An example of a cross-sectional view in which the layer 330 is omitted is illustrated in FIG.

Note that the silicon substrate 300 may be an SOI substrate. Further, instead of the silicon substrate 300, germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, or an organic semiconductor substrate can be used.

Here, an insulator 380 is provided between the layer 310 including the transistor 351 and the photodiode 360 and the layer 330 including the transistor 352 and the transistor 353. However, the position of the insulator 380 is not limited.

Hydrogen in the insulator provided in the vicinity of the channel formation region of the transistor 351 has an effect of terminating the dangling bond of silicon and improving the reliability of the transistor 351. On the other hand, hydrogen in the insulator provided in the vicinity of the transistor 352, the transistor 353, and the like is one of the factors that generate carriers in the oxide semiconductor. Therefore, the reliability of the transistor 352, the transistor 353, and the like may be reduced. Therefore, in the case where a transistor including an oxide semiconductor is stacked over a transistor including a silicon-based semiconductor, an insulator 380 having a function of blocking hydrogen is preferably provided therebetween. By confining hydrogen below the insulator 380, the reliability of the transistor 351 can be improved. Further, since diffusion of hydrogen from a lower layer than the insulator 380 to an upper layer than the insulator 380 can be suppressed, reliability of the transistor 352, the transistor 353, and the like can be improved.

As the insulator 380, for example, an insulator having a function of blocking oxygen or hydrogen is used.

In the cross-sectional view in FIG. 30A, the photodiode 360 provided in the layer 310 and the transistor provided in the layer 330 can be formed to overlap with each other. Then, the integration degree of pixels can be increased. That is, the resolution of the imaging device can be increased.

Further, as illustrated in FIGS. 31A1 and 31B1, part or all of the imaging device may be curved. FIG. 31A1 illustrates a state where the imaging device is curved in the direction of dashed-dotted line X1-X2 in FIG. FIG. 31A2 is a cross-sectional view illustrating a portion indicated by dashed-dotted line X1-X2 in FIG. FIG. 31A3 is a cross-sectional view illustrating a portion indicated by dashed-dotted line Y1-Y2 in FIG.

FIG. 31B1 illustrates a state in which the imaging device is curved in the direction of the alternate long and short dash line X3-X4 in the drawing and in the direction of the dashed dotted line Y3-Y4 in the same drawing. FIG. 31B2 is a cross-sectional view illustrating a portion indicated by dashed-dotted line X3-X4 in FIG. FIG. 31B3 is a cross-sectional view illustrating a portion indicated by dashed-dotted line Y3-Y4 in FIG.

By curving the imaging device, field curvature and astigmatism can be reduced. Therefore, optical design of a lens or the like used in combination with the imaging device can be facilitated. For example, since the number of lenses for correcting aberrations can be reduced, it is possible to reduce the size and weight of the imaging device and the like. In addition, the quality of the captured image can be improved.

<CPU> Hereinafter, a CPU including a semiconductor device such as the above-described transistor or the above-described memory device will be described.

FIG. 32 is a block diagram illustrating a configuration example of a CPU in which some of the above-described transistors are used.

32 includes an ALU 1191 (ALU: Arithmetic logic unit, arithmetic circuit), an ALU controller 1192, an instruction decoder 1193, an interrupt controller 1194, a timing controller 1195, a register 1196, a register controller 1197, and a bus interface 1198. A rewritable ROM 1199 and a ROM interface 1189. As the substrate 1190, a semiconductor substrate, an SOI substrate, a glass substrate, or the like is used. The ROM 1199 and the ROM interface 1189 may be provided in separate chips. Needless to say, the CPU illustrated in FIG. 32 is just an example in which the configuration is simplified, and an actual CPU may have various configurations depending on the application. For example, the configuration including the CPU or the arithmetic circuit illustrated in FIG. 32 may be a single core, and a plurality of the cores may be included, and each core may operate in parallel. Further, the number of bits that the CPU can handle with the internal arithmetic circuit or the data bus can be, for example, 8 bits, 16 bits, 32 bits, 64 bits, or the like.

Instructions input to the CPU via the bus interface 1198 are input to the instruction decoder 1193, decoded, and then input to the ALU controller 1192, interrupt controller 1194, register controller 1197, and timing controller 1195.

The ALU controller 1192, interrupt controller 1194, register controller 1197, and timing controller 1195 perform various controls based on the decoded instructions. Specifically, the ALU controller 1192 generates a signal for controlling the operation of the ALU 1191. The interrupt controller 1194 determines and processes an interrupt request from an external input / output device or a peripheral circuit from the priority or mask state during execution of the CPU program. The register controller 1197 generates an address of the register 1196, and reads and writes the register 1196 according to the state of the CPU.

In addition, the timing controller 1195 generates a signal for controlling the operation timing of the ALU 1191, the ALU controller 1192, the instruction decoder 1193, the interrupt controller 1194, and the register controller 1197. For example, the timing controller 1195 includes an internal clock generation unit that generates an internal clock signal CLK2 based on the reference clock signal CLK1, and supplies the internal clock signal CLK2 to the various circuits.

In the CPU illustrated in FIG. 32, a memory cell is provided in the register 1196. As the memory cell of the register 1196, the above-described transistor, memory device, or the like can be used.

In the CPU shown in FIG. 32, the register controller 1197 selects a holding operation in the register 1196 in accordance with an instruction from the ALU 1191. That is, whether to hold data by a flip-flop or to hold data by a capacitor in a memory cell included in the register 1196 is selected. When data retention by the flip-flop is selected, the power supply voltage is supplied to the memory cell in the register 1196. When holding of data in the capacitor is selected, data is rewritten to the capacitor and supply of power supply voltage to the memory cells in the register 1196 can be stopped.

FIG. 33 is an example of a circuit diagram of a memory element 1200 that can be used as the register 1196. The memory element 1200 includes a circuit 1201 in which stored data is volatilized by power-off, a circuit 1202 in which stored data is not volatilized by power-off, a switch 1203, a switch 1204, a logic element 1206, a capacitor 1207, and a selection function. Circuit 1220 having. The circuit 1202 includes a capacitor 1208, a transistor 1209, and a transistor 1210. Note that the memory element 1200 may further include other elements such as a diode, a resistance element, and an inductor, as necessary.

Here, the memory device described above can be used for the circuit 1202. When supply of power supply voltage to the memory element 1200 is stopped, GND (0 V) or a potential at which the transistor 1209 is turned off is continuously input to the gate of the transistor 1209 of the circuit 1202. For example, the gate of the transistor 1209 is grounded through a load such as a resistor.

The switch 1203 is configured using a transistor 1213 of one conductivity type (eg, n-channel type), and the switch 1204 is configured using a transistor 1214 of conductivity type (eg, p-channel type) opposite to the one conductivity type. An example is shown. Here, the first terminal of the switch 1203 corresponds to one of the source and the drain of the transistor 1213, the second terminal of the switch 1203 corresponds to the other of the source and the drain of the transistor 1213, and the switch 1203 corresponds to the gate of the transistor 1213. In accordance with the control signal RD input to the second terminal, conduction or non-conduction between the first terminal and the second terminal (that is, the conduction state or non-conduction state of the transistor 1213) is selected. The first terminal of the switch 1204 corresponds to one of the source and the drain of the transistor 1214, the second terminal of the switch 1204 corresponds to the other of the source and the drain of the transistor 1214, and the switch 1204 is input to the gate of the transistor 1214. The control signal RD selects the conduction or non-conduction between the first terminal and the second terminal (that is, the conduction state or non-conduction state of the transistor 1214).

One of a source and a drain of the transistor 1209 is electrically connected to one of a pair of electrodes of the capacitor 1208 and a gate of the transistor 1210. Here, the connection part is referred to as a node M2. One of a source and a drain of the transistor 1210 is electrically connected to a wiring that can supply a low power supply potential (eg, a GND line), and the other is connected to the first terminal of the switch 1203 (the source and the drain of the transistor 1213 On the other hand). A second terminal of the switch 1203 (the other of the source and the drain of the transistor 1213) is electrically connected to a first terminal of the switch 1204 (one of the source and the drain of the transistor 1214). A second terminal of the switch 1204 (the other of the source and the drain of the transistor 1214) is electrically connected to a wiring that can supply the power supply potential VDD. A second terminal of the switch 1203 (the other of the source and the drain of the transistor 1213), a first terminal of the switch 1204 (one of a source and a drain of the transistor 1214), an input terminal of the logic element 1206, and the capacitor 1207 One of the pair of electrodes is electrically connected. Here, the connection part is referred to as a node M1. The other of the pair of electrodes of the capacitor 1207 can be configured to receive a constant potential. For example, a low power supply potential (such as GND) or a high power supply potential (such as VDD) can be input. The other of the pair of electrodes of the capacitor 1207 is electrically connected to a wiring (eg, a GND line) that can supply a low power supply potential. The other of the pair of electrodes of the capacitor 1208 can have a constant potential. For example, a low power supply potential (such as GND) or a high power supply potential (such as VDD) can be input. The other of the pair of electrodes of the capacitor 1208 is electrically connected to a wiring (eg, a GND line) that can supply a low power supply potential.

Note that the capacitor 1207 and the capacitor 1208 can be omitted by positively using a parasitic capacitance of a transistor or a wiring.

A control signal WE is input to the gate of the transistor 1209. The switch 1203 and the switch 1204 are selected to be in a conductive state or a non-conductive state between the first terminal and the second terminal by a control signal RD different from the control signal WE. When the terminals of the other switch are in a conductive state, the first terminal and the second terminal of the other switch are in a non-conductive state.

A signal corresponding to data held in the circuit 1201 is input to the other of the source and the drain of the transistor 1209. FIG. 33 illustrates an example in which the signal output from the circuit 1201 is input to the other of the source and the drain of the transistor 1209. A signal output from the second terminal of the switch 1203 (the other of the source and the drain of the transistor 1213) is an inverted signal obtained by inverting the logic value by the logic element 1206 and is input to the circuit 1201 through the circuit 1220. .

Note that FIG. 33 illustrates an example in which a signal output from the second terminal of the switch 1203 (the other of the source and the drain of the transistor 1213) is input to the circuit 1201 through the logic element 1206 and the circuit 1220. It is not limited to. A signal output from the second terminal of the switch 1203 (the other of the source and the drain of the transistor 1213) may be input to the circuit 1201 without inversion of the logical value. For example, when there is a node in the circuit 1201 that holds a signal in which the logical value of the signal input from the input terminal is inverted, the second terminal of the switch 1203 (the other of the source and the drain of the transistor 1213) An output signal can be input to the node.

In FIG. 33, among the transistors used for the memory element 1200, a transistor other than the transistor 1209 can be a transistor whose channel is formed in a film or a substrate 1190 made of a semiconductor other than an oxide semiconductor. For example, a transistor in which a channel is formed in a silicon film or a silicon substrate can be used. Further, all the transistors used for the memory element 1200 can be transistors whose channels are formed using an oxide semiconductor. Alternatively, the memory element 1200 may include a transistor whose channel is formed using an oxide semiconductor in addition to the transistor 1209, and the remaining transistors are formed using a semiconductor layer other than the oxide semiconductor or the substrate 1190. It can also be a transistor.

For the circuit 1201 in FIG. 33, for example, a flip-flop circuit can be used. As the logic element 1206, for example, an inverter, a clocked inverter, or the like can be used.

In the semiconductor device according to one embodiment of the present invention, data stored in the circuit 1201 can be held by the capacitor 1208 provided in the circuit 1202 while the power supply voltage is not supplied to the memory element 1200.

In addition, a transistor in which a channel is formed in an oxide semiconductor has extremely low off-state current. For example, the off-state current of a transistor in which a channel is formed in an oxide semiconductor is significantly lower than the off-state current of a transistor in which a channel is formed in crystalline silicon. Therefore, by using the transistor as the transistor 1209, the signal held in the capacitor 1208 is maintained for a long time even when the power supply voltage is not supplied to the memory element 1200. In this manner, the memory element 1200 can hold stored data (data) even while the supply of power supply voltage is stopped.

Further, by providing the switch 1203 and the switch 1204, the memory element is characterized by performing a precharge operation; therefore, after the supply of power supply voltage is resumed, the time until the circuit 1201 retains the original data again is shortened. be able to.

In the circuit 1202, the signal held by the capacitor 1208 is input to the gate of the transistor 1210. Therefore, after the supply of the power supply voltage to the memory element 1200 is restarted, the signal held by the capacitor 1208 is converted into the state of the transistor 1210 (a conductive state or a non-conductive state) and read from the circuit 1202 Can do. Therefore, the original signal can be accurately read even if the potential corresponding to the signal held in the capacitor 1208 slightly fluctuates.

By using such a storage element 1200 for a storage device such as a register or a cache memory included in the processor, loss of data in the storage device due to stop of supply of power supply voltage can be prevented. In addition, after the supply of the power supply voltage is resumed, the state before the power supply stop can be restored in a short time. Accordingly, power can be stopped in a short time in the entire processor or in one or a plurality of logic circuits constituting the processor, so that power consumption can be suppressed.

Although the memory element 1200 has been described as an example of use for a CPU, the memory element 1200 can be applied to an LSI such as a DSP (Digital Signal Processor), a custom LSI, or a PLD (Programmable Logic Device), and an RF (Radio Frequency Device) device. .

<Display Device> A display device according to one embodiment of the present invention will be described below with reference to FIGS.

As a display element used for the display device, a liquid crystal element (also referred to as a liquid crystal display element), a light-emitting element (also referred to as a light-emitting display element), or the like can be used. The light-emitting element includes, in its category, an element whose luminance is controlled by current or voltage, and specifically includes inorganic EL (Electroluminescence), organic EL, and the like. Hereinafter, a display device using an EL element (an EL display device) and a display device using a liquid crystal element (a liquid crystal display device) will be described as examples of the display device.

Note that a display device described below includes a panel in which a display element is sealed, and a module in which an IC or the like including a controller is mounted on the panel.

The display device described below refers to an image display device or a light source (including a lighting device). The display device includes all connectors, for example, a module to which FPC and TCP are attached, a module having a printed wiring board at the end of TCP, or a module in which an IC (integrated circuit) is directly mounted on a display element by a COG method.

FIG. 34 illustrates an example of an EL display device according to one embodiment of the present invention. FIG. 34A shows a circuit diagram of a pixel of an EL display device. FIG. 34B is a top view showing the entire EL display device. FIG. 34C is an MN cross section corresponding to part of the dashed-dotted line MN in FIG.

FIG. 34A is an example of a circuit diagram of a pixel used in the EL display device.

Note that in this specification and the like, a person skilled in the art can connect all terminals of an active element (a transistor, a diode, etc.), a passive element (a capacitor element, a resistance element, etc.) without specifying connection destinations. Thus, it may be possible to constitute an aspect of the invention. That is, it can be said that one aspect of the invention is clear without specifying the connection destination. And, when the content specifying the connection destination is described in this specification etc., it is possible to determine that one aspect of the invention that does not specify the connection destination is described in this specification etc. There is. In particular, when a plurality of locations are assumed as the connection destination of the terminal, it is not necessary to limit the connection destination of the terminal to a specific location. Therefore, it is possible to constitute one embodiment of the present invention by specifying connection destinations of only some terminals of active elements (transistors, diodes, etc.) and passive elements (capacitance elements, resistance elements, etc.). There are cases.

Note that in this specification and the like, it may be possible for those skilled in the art to specify the invention when at least the connection portion of a circuit is specified. Alternatively, it may be possible for those skilled in the art to specify the invention when at least the function of a circuit is specified. That is, if the function is specified, it can be said that one aspect of the invention is clear. Then, it may be possible to determine that one embodiment of the invention whose function is specified is described in this specification and the like. Therefore, if a connection destination is specified for a certain circuit without specifying a function, the circuit is disclosed as one embodiment of the invention, and can constitute one embodiment of the invention. Alternatively, if a function is specified for a certain circuit without specifying a connection destination, the circuit is disclosed as one embodiment of the invention, and can constitute one embodiment of the invention.

The EL display device illustrated in FIG. 34A includes a switch element 743, a transistor 741, a capacitor 742, and a light-emitting element 719.

Note that FIG. 34A is an example of a circuit configuration, and thus transistors can be added. Conversely, a transistor, a switch, a passive element, or the like may not be added at each node in FIG.

A gate of the transistor 741 is electrically connected to one end of the switch element 743 and one electrode of the capacitor 742. A source of the transistor 741 is electrically connected to the other electrode of the capacitor 742 and electrically connected to one electrode of the light-emitting element 719. The source of the transistor 741 is supplied with the power supply potential VDD. The other end of the switch element 743 is electrically connected to the signal line 744. A constant potential is applied to the other electrode of the light-emitting element 719. Note that the constant potential is set to the ground potential GND or lower.

As the switch element 743, a transistor is preferably used. By using a transistor, the area of a pixel can be reduced and an EL display device with high resolution can be obtained. In addition, when a transistor manufactured through the same process as the transistor 741 is used as the switch element 743, the productivity of the EL display device can be increased. Note that as the transistor 741 and / or the switch element 743, for example, the above-described transistor can be used.

FIG. 34B is a top view of the EL display device. The EL display device includes a substrate 700, a substrate 750, a sealant 734, a driver circuit 735, a driver circuit 736, a pixel 737, and an FPC 732. The sealant 734 is disposed between the substrate 700 and the substrate 750 so as to surround the pixel 737, the drive circuit 735, and the drive circuit 736. Note that the drive circuit 735 and / or the drive circuit 736 may be disposed outside the sealant 734.

FIG. 34C is a cross-sectional view of the EL display device corresponding to part of the dashed-dotted line MN in FIG.

In FIG. 34C, the transistor 741 includes a conductor 704a over the substrate 700, an insulator 712a over the conductor 704a, an insulator 712b over the insulator 712a, and a conductor 704a over the insulator 712b. Semiconductors 706a and 706b overlapping with each other, conductors 716a and 716b in contact with the semiconductors 706a and 706b, insulators 718a on the semiconductor 706b, conductors 716a and 716b, and insulators on the insulator 718a A structure including a body 718b, an insulator 718c over the insulator 718b, and a conductor 714a over the insulator 718c and overlapping with the semiconductor 706b is illustrated. Note that the structure of the transistor 741 is just an example, and a structure different from the structure illustrated in FIG.

Therefore, in the transistor 741 illustrated in FIG. 34C, the conductor 704a functions as a gate electrode, the insulators 712a and 712b function as gate insulators, and the conductor 716a includes a source electrode. The conductor 716b functions as a drain electrode, the insulator 718a, the insulator 718b, and the insulator 718c function as a gate insulator, and the conductor 714a functions as a gate electrode. It has a function. Note that the electrical characteristics of the semiconductor 706 may fluctuate when exposed to light. Therefore, it is preferable that one or more of the conductor 704a, the conductor 716a, the conductor 716b, and the conductor 714a have a light-blocking property.

Note that although the interface between the insulator 718a and the insulator 718b is represented by a broken line, this indicates that the boundary between them may not be clear. For example, when the same kind of insulator is used as the insulator 718a and the insulator 718b, the two may not be distinguished depending on the observation technique.

In FIG. 34C, the capacitor 742 includes the conductor 704b over the substrate, the insulator 712a over the conductor 704b, the insulator 712b over the insulator 712a, and the conductor 704b over the insulator 712b. A conductor 716a overlapping with the conductor 716a, an insulator 718a over the conductor 716a, an insulator 718b over the insulator 718a, an insulator 718c over the insulator 718b, and a conductor overlying the conductor 716a over the insulator 718c. 714b, and in the region where the conductor 716a and the conductor 714b overlap with each other, part of the insulator 718a and the insulator 718b is removed.

In the capacitor 742, the conductor 704b and the conductor 714b function as one electrode, and the conductor 716a functions as the other electrode.

Therefore, the capacitor 742 can be manufactured using a film in common with the transistor 741. The conductors 704a and 704b are preferably the same kind of conductors. In that case, the conductor 704a and the conductor 704b can be formed through the same process. The conductors 714a and 714b are preferably the same kind of conductors. In that case, the conductor 714a and the conductor 714b can be formed through the same process.

A capacitor 742 illustrated in FIG. 34C is a capacitor having a large capacitance per occupied area. Accordingly, FIG. 34C illustrates an EL display device with high display quality. Note that the capacitor 742 illustrated in FIG. 34C has a structure in which part of the insulator 718a and the insulator 718b is removed in order to reduce the overlapping region of the conductor 716a and the conductor 714b. The capacitor according to one embodiment is not limited to this. For example, in order to thin the region where the conductors 716a and 714b overlap with each other, a structure in which part of the insulator 718c is removed may be employed.

An insulator 720 is provided over the transistor 741 and the capacitor 742. Here, the insulator 720 may have an opening reaching the conductor 716a functioning as a source electrode of the transistor 741. A conductor 781 is provided over the insulator 720. The conductor 781 may be electrically connected to the transistor 741 through the opening of the insulator 720.

A partition 784 having an opening reaching the conductor 781 is provided over the conductor 781. A light-emitting layer 782 that is in contact with the conductor 781 through the opening of the partition 784 is provided over the partition 784. A conductor 783 is provided over the light-emitting layer 782. A region where the conductor 781, the light emitting layer 782, and the conductor 783 overlap with each other serves as the light emitting element 719.

Up to this point, an example of an EL display device has been described. Next, an example of a liquid crystal display device will be described.

FIG. 35A is a circuit diagram illustrating a configuration example of a pixel of a liquid crystal display device. The pixel shown in FIG. 35 includes a transistor 751, a capacitor 752, and an element (liquid crystal element) 753 filled with liquid crystal between a pair of electrodes.

In the transistor 751, one of a source and a drain is electrically connected to the signal line 755 and a gate is electrically connected to the scanning line 754.

In the capacitor 752, one electrode is electrically connected to the other of the source and the drain of the transistor 751, and the other electrode is electrically connected to a wiring for supplying a common potential.

In the liquid crystal element 753, one electrode is electrically connected to the other of the source and the drain of the transistor 751, and the other electrode is electrically connected to a wiring for supplying a common potential. Note that the common potential applied to the wiring to which the other electrode of the capacitor 752 is electrically connected may be different from the common potential applied to the other electrode of the liquid crystal element 753.

Note that the top view of the liquid crystal display device is the same as that of the EL display device. A cross-sectional view of the liquid crystal display device corresponding to the dashed-dotted line MN in FIG. 34B is illustrated in FIG. In FIG. 35B, the FPC 732 is connected to a wiring 733a through a terminal 731. Note that the wiring 733a may be formed using the same kind of conductor or semiconductor as the conductor or semiconductor included in the transistor 751.

The description of the transistor 741 is referred to for the transistor 751. For the capacitor 752, the description of the capacitor 742 is referred to. Note that FIG. 35B illustrates a structure of the capacitor 752 corresponding to the capacitor 742 in FIG. 34C; however, the structure is not limited thereto.

Note that in the case where an oxide semiconductor is used for the semiconductor of the transistor 751, a transistor with extremely low off-state current can be obtained. Therefore, the charge held in the capacitor 752 is unlikely to leak, and the voltage applied to the liquid crystal element 753 can be maintained for a long time. Therefore, when a moving image or a still image with little movement is displayed, the transistor 751 is turned off, so that power for the operation of the transistor 751 is not necessary and a liquid crystal display device with low power consumption can be obtained. In addition, since the area occupied by the capacitor 752 can be reduced, a liquid crystal display device with a high aperture ratio or a liquid crystal display device with high definition can be provided.

An insulator 721 is provided over the transistor 751 and the capacitor 752. Here, the insulator 721 has an opening reaching the transistor 751. A conductor 791 is provided over the insulator 721. The conductor 791 is electrically connected to the transistor 751 through the opening of the insulator 721.

An insulator 792 functioning as an alignment film is provided over the conductor 791. A liquid crystal layer 793 is provided over the insulator 792. An insulator 794 functioning as an alignment film is provided over the liquid crystal layer 793. A spacer 795 is provided over the insulator 794. A conductor 796 is provided over the spacer 795 and the insulator 794. A substrate 797 is provided over the conductor 796.

With the above structure, a display device including a capacitor with a small occupied area can be provided, or a display device with high display quality can be provided. Alternatively, a high-definition display device can be provided.

For example, in this specification and the like, a display element, a display device that is a device including a display element, a light-emitting element, and a light-emitting device that is a device including a light-emitting element have various forms or have various elements. Can do. Examples of display elements, display devices, light-emitting elements, or light-emitting devices include white, red, green, and blue light-emitting diodes (LEDs), transistors (transistors that emit light in response to current), electron-emitting devices, Liquid crystal element, electronic ink, electrophoretic element, grating light valve (GLV), plasma display (PDP), display element using MEMS (micro electro mechanical system), digital micromirror device (DMD), DMS (digital)・ Micro shutter), IMOD (interference modulation) element, shutter type MEMS display element, optical interference type MEMS display element, electrowetting element, piezoelectric ceramic display, carbo At least one of display elements using carbon nanotubes. In addition to these, a display medium in which contrast, luminance, reflectance, transmittance, and the like are changed by an electric or magnetic action may be included.

An example of a display device using an EL element is an EL display. As an example of a display device using an electron-emitting device, there is a field emission display (FED), a SED type planar display (SED: Surface-Conduction Electron-Emitter Display), or the like. As an example of a display device using a liquid crystal element, there is a liquid crystal display (a transmissive liquid crystal display, a transflective liquid crystal display, a reflective liquid crystal display, a direct view liquid crystal display, a projection liquid crystal display) and the like. An example of a display device using electronic ink, electronic powder fluid (registered trademark), or an electrophoretic element is electronic paper. Note that in the case of realizing a transflective liquid crystal display or a reflective liquid crystal display, part or all of the pixel electrode may have a function as a reflective electrode. For example, part or all of the pixel electrode may have aluminum, silver, or the like. Further, in that case, a memory circuit such as an SRAM can be provided under the reflective electrode. Thereby, power consumption can be further reduced.

In addition, when using LED, you may arrange | position graphene or graphite under the electrode and nitride semiconductor of LED. Graphene or graphite may be a multilayer film in which a plurality of layers are stacked. Thus, by providing graphene or graphite, a nitride semiconductor such as an n-type GaN semiconductor having a crystal can be easily formed thereon. Furthermore, a p-type GaN semiconductor having a crystal or the like can be provided thereon to form an LED. Note that an AlN layer may be provided between graphene or graphite and an n-type GaN semiconductor having a crystal. Note that the GaN semiconductor included in the LED may be formed by MOCVD. However, by providing graphene, the GaN semiconductor included in the LED can be formed by a sputtering method.

<Electronic Device> A semiconductor device according to one embodiment of the present invention reproduces a recording medium such as a display device, a personal computer, and a recording medium (typically a DVD: Digital Versatile Disc) and displays the image. It can be used for a device having a display capable of displaying. In addition, as an electronic device in which the semiconductor device according to one embodiment of the present invention can be used, a mobile phone, a game machine including a portable type, a portable data terminal, an electronic book terminal, a video camera, a digital still camera, or the like, goggles Type displays (head-mounted displays), navigation systems, sound playback devices (car audio, digital audio players, etc.), copiers, facsimiles, printers, multifunction printers, automated teller machines (ATMs), vending machines, etc. It is done. Specific examples of these electronic devices are shown in FIGS.

FIG. 36A illustrates a portable game machine including a housing 901, a housing 902, a display portion 903, a display portion 904, a microphone 905, a speaker 906, operation keys 907, a stylus 908, and the like. Note that although the portable game machine illustrated in FIG. 36A includes two display portions 903 and 904, the number of display portions included in the portable game device is not limited thereto.

FIG. 36B illustrates a portable data terminal, which includes a first housing 911, a second housing 912, a first display portion 913, a second display portion 914, a connection portion 915, operation keys 916, and the like. The first display unit 913 is provided in the first housing 911, and the second display unit 914 is provided in the second housing 912. The first housing 911 and the second housing 912 are connected by the connection portion 915, and the angle between the first housing 911 and the second housing 912 can be changed by the connection portion 915. is there. It is good also as a structure which switches the image | video in the 1st display part 913 according to the angle between the 1st housing | casing 911 and the 2nd housing | casing 912 in the connection part 915. FIG. In addition, a display device in which a function as a position input device is added to at least one of the first display portion 913 and the second display portion 914 may be used. Note that the function as a position input device can be added by providing a touch panel on the display device. Alternatively, the function as a position input device can be added by providing a photoelectric conversion element called a photosensor in a pixel portion of a display device.

FIG. 36C illustrates a laptop personal computer, which includes a housing 921, a display portion 922, a keyboard 923, a pointing device 924, and the like.

FIG. 36D illustrates an electric refrigerator-freezer, which includes a housing 931, a refrigerator door 932, a refrigerator door 933, and the like.

FIG. 36E illustrates a video camera, which includes a first housing 941, a second housing 942, a display portion 943, operation keys 944, a lens 945, a connection portion 946, and the like. The operation key 944 and the lens 945 are provided in the first housing 941, and the display portion 943 is provided in the second housing 942. The first housing 941 and the second housing 942 are connected by a connection portion 946, and the angle between the first housing 941 and the second housing 942 can be changed by the connection portion 946. is there. It is good also as a structure which switches the image | video in the display part 943 according to the angle between the 1st housing | casing 941 and the 2nd housing | casing 942 in the connection part 946. FIG.

FIG. 36F illustrates an automobile, which includes a vehicle body 951, wheels 952, a dashboard 953, lights 954, and the like.

  In this example, an oxide semiconductor film used for the semiconductor device according to one embodiment of the present invention is formed, and the oxide semiconductor film is subjected to X-ray diffraction (XRD) measurement and transmission electron. The result observed using the microscope (TEM: transmission electron microscope) is demonstrated.

  In this embodiment, a silicon oxide film is formed on a silicon substrate with a thickness of 100 nm, and an oxide semiconductor film (IGZO film) is formed on the silicon oxide film with a thickness of 40 nm. Thru | or E were produced.

  Here, the silicon oxide film is a thermal oxide film, and was formed by performing heat treatment at a temperature of 950 ° C. in an oxygen atmosphere containing 3% HCl.

The oxide semiconductor film is an In—Ga—Zn—O-based oxide semiconductor film and was formed by a sputtering method. The deposition conditions of the oxide semiconductor film are as follows: an oxide target having a composition of In: Ga: Zn = 1: 3: 4 (atomic ratio), a deposition gas flow rate Ar: 40 sccm, O ₂ : 5 sccm, The film was formed with a pressure of 0.7 Pa, a substrate temperature of 200 ° C., a direct current (DC) power supply power of 0.5 kW, and a distance between the target and the substrate of 60 mm.

For Samples A to D, oxygen ions ( ¹⁶ O ⁺ ) were implanted into the oxide semiconductor film by an ion implantation method. The ion implantation conditions were an acceleration voltage of 5 kV, a dose of 1.0 × 10 ¹⁶ ions / cm ² , a tilt angle of 0 °, and a twist angle of 0 °.

Note that the acceleration voltage may be 0.2 kV or more and 250 kV or less, more preferably 0.2 kV or more and 60 kV or less. The dose may be 1.0 × 10 ¹¹ ions / cm ² or more and 5.0 × 10 ¹⁶ ions / cm ² .

  Here, samples A to C were ion-implanted while heating the substrate using a heater provided in the substrate holder of the ion implantation apparatus. The substrate heating temperatures were 450 ° C. for sample A, 350 ° C. for sample B, and 250 ° C. for sample C. Sample D was subjected to ion implantation without heating the substrate, but the substrate temperature rose to about 40 ° C. to 50 ° C. during the ion implantation. The samples A to C and the sample D were subjected to ion implantation using different ion implantation apparatuses under the same ion implantation conditions.

  FIG. 46 shows the result of XRD measurement performed on samples A to E using the powder method. In this example, the XRD spectrum was measured using out-of-plane measurement. FIG. 46 shows normalized strength [a. u. ] And the horizontal axis represents the diffraction angle 2θ [deg. ].

As shown in FIG. 46, samples A to E have a peak in the vicinity of 2θ = 31 °, and the peak becomes broader from sample A to sample D. This peak belongs to the (009) plane of the InGaZnO ₄ crystal and represents the c-axis orientation of the CAAC-OS crystal. In other words, it can be said that the c-axis orientation of the oxide semiconductor film crystal decreases as the substrate temperature during ion implantation decreases.

  As shown in FIG. 46, only the sample D has a peak in the vicinity of 2θ = 36 °. A peak near 2θ = 36 ° indicates that a crystal having no c-axis alignment is included in part of the CAAC-OS. That is, in comparison with Samples A to C in which ions are implanted while heating the substrate, Sample D in which ions are implanted at room temperature has a lower c-axis orientation of the oxide semiconductor film crystal. it can.

  In this example, samples F to I were further produced, and cross-sectional TEM images were taken. Here, Samples F to J are the same as Samples A to E except that the oxide semiconductor film is formed to have a thickness of 20 nm. Sample F is Sample A and Sample G is Sample B. Sample H corresponds to Sample C, and Sample I corresponds to Sample D.

  47 and 48 show cross-sectional TEM images of Samples E to I taken using a TEM. 47A is a cross-sectional TEM image of sample F at a magnification of 80000 times, FIG. 47B is a cross-sectional TEM image of sample G at a magnification of 80000 times, and FIG. FIG. 48B is a cross-sectional TEM image of Sample I at a magnification of 80000 times. In this example, the cross-sectional TEM image was taken with an acceleration voltage of 300 kV.

  As shown in FIGS. 47A and 47B and FIG. 48A, in the oxide semiconductor films of Samples F to H, CAAC-OS crystals are arranged in a layer shape substantially parallel to the formation surface. And has a high c-axis orientation. On the other hand, as shown in FIG. 48B, in the oxide semiconductor film of Sample I, crystals arranged in layers are seen, but a region surrounded by an ellipse is inclined with respect to a formation surface. Many crystals are arranged. Thus, Sample I implanted with oxygen ions at room temperature has a low c-axis orientation of the crystal.

  From the results of the above XRD measurement and cross-sectional TEM image observation, the substrate temperature at the time of oxygen ion implantation can be greater than 60 ° C. and 500 ° C. or less, more preferably 100 ° C. or more and 500 ° C. or less.

  From the above, it was shown that oxygen ions can be implanted while maintaining the c-axis orientation of the oxide semiconductor film high by performing oxygen ion implantation of the oxide semiconductor film while heating the substrate.

101 Substrate Holding Member 102 Substrate 105 Layer 103 Heater 120 Oxygen Ion 132 Excess Oxygen 200 Imaging Device 201 Switch 202 Switch 203 Switch 210 Pixel Unit 211 Pixel 212 Subpixel 212B Subpixel 212G Subpixel 212R Subpixel 220 Photoelectric Conversion Element 230 Pixel Circuit 231 Wiring 247 wiring 248 wiring 249 wiring 250 wiring 253 wiring 254 filter 254B filter 254G filter 254R filter 255 lens 256 light 257 wiring 260 peripheral circuit 270 peripheral circuit 280 peripheral circuit 290 peripheral circuit 291 light source 300 silicon substrate 310 layer 320 layer 330 layer 340 layer 351 Transistor 352 Transistor 353 Transistor 360 Photodiode 361 Anode 363 Low resistance region 370 Plug 37 Wiring 372 wiring 373 wiring 380 insulator 400 substrate 401 insulator 402 insulator 404 conductor 406 semiconductor 406a semiconductor 406b semiconductor 413 conductor 416a conductor 416b conductor 434 conductor 436c semiconductor 442 insulator 450 semiconductor substrate 452 insulator 454 conductor Body 456 region 460 region 462 insulator 464 insulator 466 insulator 468 insulator 472a region 472b region 474a conductor 474b conductor 474c conductor 476a conductor 476b conductor 478a conductor 478b conductor 478c conductor 480a conductor 480b Body 480c conductor 490 insulator 492 insulator 494 insulator 496a conductor 496b conductor 496c conductor 496d conductor 498a conductor 498b conductor 498c conductor 498d conductor Body 500 substrate 502 insulator 503 insulator 504 conductor 506a semiconductor 506b semiconductor 506c semiconductor 511 insulator 512 insulator 513 conductor 514 conductor 516 conductor 516a conductor 516b conductor 534 conductor 536a semiconductor 536b semiconductor 536c semiconductor 542 insulator Body 700 substrate 704a conductor 704b conductor 706 semiconductor 706a semiconductor 706b semiconductor 712a insulator 712b insulator 714a conductor 714b conductor 716a conductor 716b conductor 718a insulator 718b insulator 718c insulator 719 light emitting element 720 insulator 721 insulator Body 731 Terminal 732 FPC
733a wiring 734 sealant 735 drive circuit 736 drive circuit 737 pixel 741 transistor 742 capacitor element 743 switch element 744 signal line 750 substrate 751 transistor 752 capacitor element 753 liquid crystal element 754 scan line 755 signal line 781 conductor 782 light emitting layer 783 conductor 784 Partition 791 Conductor 792 Insulator 793 Liquid crystal layer 794 Insulator 795 Spacer 796 Conductor 797 Substrate 901 Housing 902 Housing 903 Display portion 904 Display portion 905 Microphone 906 Speaker 907 Operation key 908 Stylus 911 Housing 912 Housing 913 Display portion 914 Display unit 915 Connection unit 916 Operation key 921 Case 922 Display unit 923 Keyboard 924 Pointing device 931 Case 932 Refrigeration room door 933 Freezer compartment door 941 Case 42 housing 943 display unit 944 operation keys 945 lens 946 connecting portions 951 body 952 wheel 953 dashboard 954 Light 1189 ROM interface 1190 substrate 1191 ALU
1192 ALU Controller 1193 Instruction Decoder 1194 Interrupt Controller 1195 Timing Controller 1196 Register 1197 Register Controller 1198 Bus Interface 1199 ROM
1200 Memory element 1201 Circuit 1202 Circuit 1203 Switch 1204 Switch 1206 Logic element 1207 Capacitor element 1208 Capacitor element 1209 Transistor 1210 Transistor 1213 Transistor 1214 Transistor 1220 Circuit 2100 Transistor 2200 Transistor 3001 Wiring 3002 Wiring 3003 Wiring 3004 Wiring 3005 Wiring 3200 Transistor 3300 Capacitor 3400 Capacitor Element 5100 Pellet 5120 Substrate 5161 Region 5200 Pellet 5201 Ion 5203 Particle 5206 Oxide thin film 5220 Substrate 5230 Target 5240 Plasma

Claims (15)

An oxide semiconductor layer having crystallinity is formed over a substrate;
Adding oxygen to the oxide semiconductor layer while heating the substrate;
A method for manufacturing a semiconductor device, wherein a semiconductor element including the oxide semiconductor layer is formed.   2. The method for manufacturing a semiconductor device according to claim 1, wherein the addition of oxygen is performed by an ion implantation method.   The method for manufacturing a semiconductor device according to claim 1, wherein heat treatment is performed after oxygen is added to the oxide semiconductor.   2. The semiconductor device according to claim 1, wherein the oxide semiconductor layer contains indium, an element M (Ti, Ga, Y, Zr, La, Ce, Nd, Sn, or Hf), zinc, and oxygen. Method.   The method for manufacturing a semiconductor device according to claim 1, wherein the temperature of the substrate when oxygen is added is 60 ° C. or higher and 500 ° C. or lower. Forming a conductor on the substrate,
Depositing a first insulator on the conductor;
Forming an oxide semiconductor having crystallinity on the conductor through the first insulator;
Forming a second insulator over the oxide semiconductor;
Depositing a third insulator on the second insulator;
A method for manufacturing a semiconductor device, wherein fluorine is added to the second insulator through the third insulator while the substrate is heated. In claim 6,
The method for manufacturing a semiconductor device, wherein the second insulator is an insulator containing oxygen and silicon. In claim 6,
The method for manufacturing a semiconductor device, wherein the third insulator is an insulator including nitrogen and silicon.   The method for manufacturing a semiconductor device according to claim 6, wherein the addition of fluorine is performed by an ion implantation method.   7. The semiconductor device according to claim 6, wherein the oxide semiconductor layer contains indium, an element M (Ti, Ga, Y, Zr, La, Ce, Nd, Sn, or Hf), zinc, and oxygen. Method.   The method for manufacturing a semiconductor device according to claim 6, wherein the temperature of the substrate when oxygen is added is 60 ° C. or higher and 500 ° C. or lower. An oxide semiconductor layer having crystallinity is formed over a substrate;
Forming a semiconductor element having the oxide semiconductor layer;
Forming a barrier layer on the semiconductor element;
A method for manufacturing a semiconductor device, wherein fluorine is added to the barrier layer while the substrate is heated.   The method for manufacturing a semiconductor device according to claim 12, wherein the barrier layer is an insulator containing oxygen and aluminum.   The semiconductor device according to claim 12, wherein the oxide semiconductor layer contains indium, an element M (Ti, Ga, Y, Zr, La, Ce, Nd, Sn, or Hf), zinc, and oxygen. Manufacturing method.   The method for manufacturing a semiconductor device according to claim 12, wherein the temperature of the substrate when oxygen is added is 60 ° C. or higher and 500 ° C. or lower.

Images