JPWO2006022453A1 - GaN-based field effect transistor and manufacturing method thereof - Google Patents

Abstract

An object of the present invention is to provide a GaN-based heterojunction transistor that can achieve high output, high breakdown voltage, high speed, high frequency, and the like. The above-described problem is a field effect transistor having a heterostructure including a channel layer (4) made of GaN and a barrier layer (6) made of AlGaN, and includes a field effect transistor having an insulating film (10) on the surface of the transistor element. Solved.

Description

  The present invention relates to a field effect transistor having a hetero structure with high output, high breakdown voltage, high speed, and high frequency characteristics.

A heterojunction field effect transistor (FET) is a transistor having an interface (heterointerface) made of two materials having different physical properties such as a lattice constant and using a two-dimensional electron gas formed at the heterointerface as a channel. As one of heterojunction FETs, GaN-based FETs are known. AlGaN / GaN heterojunction FETs are known as GaN FETs (see, for example, Patent Document 1 (Japanese Patent Laid-Open No. 2003-258005) and Patent Document 2 (Japanese Patent Laid-Open No. 2003-243424) below). This AlGaN / GaN heterojunction FET can obtain a high two-dimensional electron concentration by the polarization electric field effect. FIG. 8 shows a conceptual diagram of a general heterojunction FET. As shown in FIG. 8, the heterojunction FET includes a substrate 2, a buffer layer 3 provided on the substrate, a channel layer 4 provided on the buffer layer, and a spacer layer 5 provided on the channel layer. And a barrier layer 6 provided on the spacer layer. In general, a source electrode 7, a gate electrode 8, and a drain electrode 9 are provided.
In order to improve the effectiveness of the gate of the transistor and increase the mutual conductance (g _m ), it is desirable to reduce the thickness of the AlGaN barrier layer. However, when the thickness of the AlGaN layer is reduced, the influence of the electric field at the AlGaN surface level at the AlGaN / GaN hetero interface increases. As a result, there is a problem that the polarization effect at the heterointerface is reduced, the two-dimensional electron concentration is lowered, and the channel resistance is increased.
Therefore, in order to improve the performance of the AlGaN / GaN heterojunction transistor and cope with higher speeds and higher frequencies, the thickness of the AlGaN layer is reduced, and at the same time, the influence of the electric field at the AlGaN surface level is reduced, and the AlGaN / GaN It is effective to increase the polarization effect at the heterointerface and increase the two-dimensional electron concentration. From this point of view, a recess type FET is known in which a cap layer and a barrier layer directly under a gate electrode portion are dug down and the gate electrode is brought closer to the channel layer (for example, Non-Patent Document 1 (Yoshiaki Sano, Katsumi Kaibe, Mitsuro Mida and Takashi Egawa “Recessed Gate Nitride Semiconductor FET with High Transconductance”, Applied Physics Vol. 73, No. 3, pp. 358-362, 2004), and Patent Document 3 (Japanese Patent Laid-Open No. 2004-186679)) . As shown in FIG. 1 of Non-Patent Document 1 and FIG. 3 of Patent Document 3, in the recessed FET, portions of the barrier layer and the cap layer below the gate electrode are deeply dug.
If such a recess type FET is used, it is said that the effect of the gate can be improved with almost no reduction in the output of current and power. This recess gate structure is formed by reactive ion etching using BCl ₃ gas or the like. It is supposed to be formed by. However, in order to manufacture a recess type FET, gas ion etching is required, so the process becomes complicated. Further, since the gas species activated by the plasma are used for etching, the etched semiconductor surface is damaged. In addition, since reactive ion etching is not so accurate, it is difficult to actually obtain an FET having an appropriate recess structure with good reproducibility.

FIG. 1 is a schematic diagram showing a heterojunction FET according to a first embodiment of the present invention.
FIG. 2 is a graph showing the relationship between the film thickness of the AlGaN barrier layer, the electron mobility of the channel, the two-dimensional electron gas concentration of the channel, and the channel sheet resistance when SiN is deposited to 30 nm.
FIG. 3 is a graph showing the relationship between the film thickness of the AlGaN barrier layer, the channel electron mobility, the channel two-dimensional electron gas concentration, and the channel sheet resistance when SiN 2 nm is deposited.
FIG. 4 is a graph showing the relationship between SiN film thickness, channel electron mobility at room temperature, two-dimensional electron gas concentration, and sheet resistance in a sample with an AlGaN barrier layer film thickness of 8 nm.
FIG. 5 shows the channel mobility, two-dimensional electron gas concentration, and sheet at different temperatures on the wafer at the room temperature in the sample of 6 nm thick AlGaN barrier layer with no SiN deposited and 2 nm SiN deposited. It is a graph which shows the relationship of resistance.
FIG. 6 is a diagram illustrating a schematic configuration of an RF-MBE apparatus used in the RF-MBE method.
FIG. 7 is a schematic view showing a MIS structure heterojunction FET according to the second embodiment of the present invention.
FIG. 8 is a conceptual diagram showing an FET without an insulating film, for explaining the feature of the present invention.

An object of the present invention is to provide a GaN-based heterojunction transistor that can achieve high output, high breakdown voltage, high speed, and high frequency.
Another object of the present invention is to provide a heterojunction FET using a barrier layer having a uniform film thickness that does not have a recess structure.
Another object of the present invention is to provide a heterojunction FET having a high two-dimensional electron concentration, excellent transconductance characteristics, and a large output.
Another object of the present invention is to provide a heterojunction FET capable of high speed and high frequency by miniaturization of a gate electrode.
The present invention basically relates to a heterojunction FET in which high two-dimensional electron density and high transconductance are obtained by depositing an insulating film on the surface of an element in a GaN-based heterojunction FET, and a method for manufacturing the same.
At least one of the above problems is a GaN-based field effect transistor having a heterostructure including a channel layer and a barrier layer, which is solved by the field effect transistor according to the first aspect of the present invention having an insulating film on the transistor element surface. The Since the insulating film is provided on the element surface, the surface level of the barrier layer can be reduced, and the electric field effect of the surface level with respect to the polarization effect at the heterointerface can be reduced. As a result, the two-dimensional electron concentration is increased and a high output can be obtained. The “GaN-based FET” means an FET such as an AlGaN / GaN heterojunction FET whose channel layer composition is GaN (or InGaN).
In a preferred aspect of the field effect transistor, the insulating film is an insulating film made of any one of SiN, SiO ₂ , SiON, Al ₂ O ₃ , and AlN. A field effect transistor according to claim 1.
In a preferred embodiment of the field effect transistor, the insulating film is an insulating film made of SiN formed by a hot wire CVD method. A field effect transistor according to claim 1.
In a preferred embodiment of the field effect transistor, the change in electron mobility in a range of 20 mm from a specific position of the field effect transistor is 10% or less. A field effect transistor according to claim 1.
In a preferred embodiment of the field effect transistor, the change in secondary electron concentration in a range of 20 mm from a specific position of the field effect transistor is 10% or less. A field effect transistor according to claim 1.
In a preferred embodiment of the field effect transistor, the insulating film has a thickness of 1 nm to 1 μm. The field effect transistor according to any one of the above.
In a preferred embodiment of the field effect transistor, the insulating film is made of SiN formed by a hot wire CVD method, and the thickness of the insulating film is 1 nm to 100 nm. The field effect transistor according to any one of the above.
A preferred embodiment of the field effect transistor is the field effect transistor according to any one of the above, wherein the channel layer is made of GaN and the barrier layer is made of AlGaN.
In a preferred embodiment of the field effect transistor, the thickness of the barrier layer is 1 to 30 nm. The field effect transistor according to any one of the above.
In a preferred embodiment of the field effect transistor, the barrier layer has a thickness of 3 to 20 nm. The field effect transistor according to any one of the above.
In a preferred embodiment of the field effect transistor, the barrier layer has a thickness of 5 to 15 nm. The field effect transistor according to any one of the above.
In a preferred embodiment of the field effect transistor, the channel layer has a thickness of 100 nm to 10 μm. The field effect transistor according to any one of the above.
A preferred embodiment of the field effect transistor is a field effect transistor in which a buffer layer, a channel layer made of GaN, and a barrier layer made of AlGaN are formed in this order on a substrate, and the thickness of the barrier layer is 1 to 30 nm. And a heterojunction field effect transistor having an insulating film on the surface of the transistor element.
In a preferred aspect of the field effect transistor, the insulating film is an insulating film made of any one of SiN, SiO ₂ , SiON, Al ₂ O ₃ , and AlN. The field effect transistor according to any one of the above.
In a preferred embodiment of the field effect transistor, the insulating film is an insulating film made of SiN formed by a hot wire CVD method. The field effect transistor according to any one of the above.
In a preferred embodiment of the field effect transistor, the change in electron mobility in a range of 20 mm from a specific position of the field effect transistor is 10% or less. The field effect transistor according to any one of the above.
In a preferred embodiment of the field effect transistor, the change in secondary electron concentration in a range of 20 mm from a specific position of the field effect transistor is 10% or less. The field effect transistor according to any one of the above.
In a preferred embodiment of the field effect transistor, the insulating film has a thickness of 1 nm to 1 μm. The field effect transistor according to any one of the above.
In a preferred embodiment of the field effect transistor, the insulating film is made of SiN formed by a hot wire CVD method, and the thickness of the insulating film is 1 nm to 100 nm. The field effect transistor according to any one of the above.
A preferred embodiment of the field effect transistor is the field effect transistor according to any one of the above, wherein a spacer layer is provided between the channel layer and the barrier layer.
The second aspect of the present invention is a step of forming a buffer layer, a channel layer made of GaN, a barrier layer made of AlGaN in this order on a substrate, a step of forming a source electrode, a gate electrode, and a drain electrode, And a step of forming an insulating film on the surface of the barrier layer.
In a preferred embodiment of the method for producing a field effect transistor, the step of forming an insulating film on the surface of the barrier layer is performed using a hot wire CVD method using SiN, SiO ₂ , SiON, Al ₂ O ₃ , or AlN as a raw material. 22. The method for producing a field effect transistor having a heterostructure according to claim 21, wherein an insulating film is formed by the method.
A preferred embodiment of the method for producing a field effect transistor is the method for producing a field effect transistor having a heterostructure according to claim 21, wherein the insulating film has a thickness of 1 nm to 1 µm.
A preferred embodiment of the method for producing a field effect transistor is the method for producing a field effect transistor having a heterostructure according to claim 21, wherein the thickness of the barrier layer made of AlGaN is 3 nm to 20 nm.
The GaN-based heterojunction FET of the present invention can reduce the surface level of the barrier layer by depositing an insulating film on the surface of the barrier layer such as AlGaN as demonstrated by the examples described later. Thereby, the electric field effect of the surface state with respect to the polarization effect at the heterointerface can be reduced, and as a result, the two-dimensional electron concentration is increased and a high output can be obtained. In particular, the GaN-based heterojunction FET of the present invention preferably has a structure having a SiN insulating film formed by a hot wire CVD method, and more preferably a combination of spacer layers having a specific composition. As shown in the examples, the heterojunction FET of the present invention is more effective when the thickness of the barrier layer is reduced to 12 nm or less (particularly 10 nm or less), and lowers the maximum current and the maximum output power. Therefore, a large transconductance can be obtained.
That is, according to the present invention, it is possible to provide a heterojunction transistor that can achieve high output, high breakdown voltage, high speed, high frequency, and the like.
According to the present invention, it is possible to provide a heterojunction FET using a barrier layer having a uniform film thickness that does not have a recess structure.
According to the present invention, it is possible to provide a heterojunction FET having a high two-dimensional electron concentration, excellent mutual conductance characteristics, and a large output.
According to the present invention, it is possible to provide a heterojunction FET capable of high speed and high frequency by miniaturization of a gate electrode.

(1. Heterojunction FET)
Embodiments of the present invention will be described below with reference to the drawings. As described above, the heterojunction FET of the present invention is basically a GaN-based field effect transistor having a heterostructure including a channel layer and a barrier layer, and has a field effect transistor having an insulating film on the surface of the transistor element. By depositing an insulating film on the AlGaN barrier layer surface, the number of surface states is reduced, the polarization effect at the heterointerface is increased, the two-dimensional electron concentration is increased, and a high output can be obtained. is there. In addition, the heterojunction FET of the present invention can obtain a higher effect when the thickness of the barrier layer is thinner than that of the conventional barrier layer, and can obtain excellent transconductance without reducing the output current and power. be able to.
(1.1. Overview of heterojunction FET)
FIG. 1 is a schematic diagram showing a heterojunction FET according to a first embodiment of the present invention. As shown in FIG. 1, the heterojunction FET according to the first embodiment of the present invention includes a substrate 2, a buffer layer 3 provided on the substrate, a channel layer 4 provided on the buffer layer, It includes a spacer layer 5 provided on the channel layer and a barrier layer 6 provided on the spacer layer. As shown in FIG. 1, this embodiment is provided with a source electrode 7, a gate electrode 8, and a drain electrode 9. In addition, the element surface is stabilized by depositing the insulating film 10 on the element surface. The hetero interface is formed between the channel layer and the spacer layer. Note that an FET having a so-called MIS (Metal-Insulator-Semiconductor) structure as shown in FIG.
(1.2. Substrate)
As the substrate, a known substrate used for a GaN-based heterojunction FET can be adopted. Examples of the material for the substrate include sapphire, SiC, GaN, and AlN. Among these, sapphire is preferable.
(1.3. Buffer layer)
The buffer layer is a layer also called a buffer layer. The difference in lattice constant between sapphire substrate and GaN is as large as about 16.3%. For this reason, when a GaN layer (channel layer) is grown directly on a sapphire substrate, very high density lattice defects are generated in the GaN layer, and high quality crystals cannot be obtained. In order to avoid such a situation, a buffer layer is provided between the substrate and the GaN layer. As the composition of the buffer layer, a known buffer layer composition used for GaN-based hetero FETs in addition to AlN can be employed. Although the film thickness of a buffer layer is not specifically limited, 10 nm-1000 nm are mention | raise | lifted, Preferably it is 100 nm-500 nm, More preferably, it is 200 nm-400 nm, More preferably, it is 250 nm-350 nm.
(1.4. Channel layer)
The channel layer is a layer that forms a heterointerface. The composition of the channel layer is GaN or InGaN, preferably GaN. The film thickness of the channel layer is 100 nm to 10 μm, preferably 500 nm to 3 μm, more preferably 1 μm to 2 μm. A transistor using gallium nitride (GaN) as a channel layer can obtain a high output because the band gap of GaN is as large as about 3.4 eV. In addition, this transistor can operate at a high voltage. InGaN composition is changed to In _X Ga _1-X Assuming N, X is 0.0001 to 0.2, preferably 0.001 to 0.05.
(1.5. Spacer layer)
The spacer layer is an arbitrary thin layer provided between the channel layer and the barrier layer. The hetero interface is an interface between the channel layer and the spacer layer. The heterojunction FET according to the first embodiment of the present invention shown in FIG. 1 has a spacer layer. However, the heterojunction FET of the present invention may not have a spacer layer. In this case, the interface between the channel layer and the barrier layer becomes a heterointerface. The composition of the spacer layer includes AlN, AlGaN, InAlGaN, or GaN, preferably AlN or AlGaN, and more preferably AlN. The thickness of the spacer layer is 0.1 nm to 5 nm, preferably 0.5 nm to 3 nm, and more preferably 1 nm to 2 nm. The AlGaN composition is Al _X Ga _1-X Assuming N, X is 0.0001 to 0.9999, and preferred X is 0.1 to 0.6. InAlGaN composition is changed to In _X Al _Y Ga _1-XY When N, X is 0.0001 to 0.2, preferable X is 0.001 to 0.05, Y is 0.1 to 0.9, and preferable Y is 0. .2 to 0.6. In particular, when the insulating film is formed by a hot wire CVD method, a preferable spacer layer can be formed even if Y is 0.3 or more, 0.4 or more, or 0.45 or more.
(1.6. Barrier layer)
The barrier layer is not particularly limited as long as it has a larger band gap than the channel layer. In the heterojunction FET of the present invention, the barrier layer may be AlGaN or InAlGaN, and is particularly preferably a barrier layer made of AlGaN (AlGaN barrier layer). Further, the barrier layer may be a recess type where the gate electrode portion is dug down, but preferably the recess layer is not a recess type and the barrier layer has a certain thickness. The recess type is difficult to manufacture with good reproducibility, but can be manufactured with good reproducibility if the barrier layer has a certain thickness. Further, as will be described later, in the present invention, a high two-dimensional electron density can be achieved by the insulating layer, so that it is not necessary to adopt a complicated shape like a recess type. AlGaN composition of the AlGaN barrier layer is changed to Al _X Ga _1-X Assuming N, X is 0.0001 to 0.9999, and preferred X is 0.1 to 0.9, 0.1 to 0.5, 0.2 to 0.4, or 0. .3-0.6 may be sufficient.
Since the present invention has an insulating layer on the element surface, a high two-dimensional electron density can be maintained as shown in Examples described later. As a result, the barrier layer can be made thin and high transconductance can be achieved. Therefore, the film thickness of the barrier layer is not particularly limited, but is 1 nm to 50 nm, preferably 1 to 30 nm, more preferably 1 nm to 20 nm, still more preferably 2 nm to 15 nm, and particularly preferably 5 to 12 nm, 3 nm to 20 nm, 5 nm to 15 nm, 1 nm to 10 nm, 5 nm to 10 nm, 10 nm to 15 nm, 10 nm to 100 nm, 20 nm to 100 nm, 25 nm to 50 nm, 10 nm to 25 nm, 5 nm to 50 nm, etc. do it. As will be described later, the provision of the insulating film exerts a great effect when the thickness of the barrier layer is 20 nm or less, preferably the thickness of the barrier layer is 15 nm or less, more preferably If the thickness of the barrier layer is 12 nm or less, the effect that a large mutual conductance can be obtained without lowering the maximum current and the maximum output power can be exhibited.
(1.7. Electrode)
As an electrode used for the heterojunction FET of the present invention, a known electrode used for the heterojunction FET can be adopted. Such an electrode includes a source electrode 7, a gate electrode 8, and a drain electrode 9.
(1.8. Insulating film)
The insulating film is a film formed on the surface of the transistor element, and stabilizes the surface of the chemically and electrically active AlGaN barrier layer. The insulating film is SiN, SiO ₂ , SiON, Al ₂ O ₃ Or any one or more of AlN. The insulating film is preferably made of any of these materials. Of these, the preferred material is SiN. In particular, an insulating film made of SiN formed by a hot wire CVD method is preferable. According to the insulating film, the two-dimensional electron density of the FET can be increased, the mutual conductance can be increased, and the output of the FET can be increased. In addition, by covering the surface of the AlGaN barrier layer with an insulating film, deterioration due to oxidation or the like can be prevented, and the operation of the element can be kept stable for a long period. That is, the insulating film also functions as a surface stabilization protective film of the element.
Although the average film thickness of the insulating film depends on the composition of the insulating film, in order to ensure the function of the insulating film, for example, 1 nm to 1 μm is given, and may be 10 nm to 500 nm, 10 nm to 300 nm, or 20 nm to 40 nm. However, it is preferably 20 nm to 200 nm. In the case of a field effect transistor having a so-called MIS (Metal Insulator Semiconductor) structure as shown in FIG. 7 described later, a thin insulating film is preferable, and an average film thickness of the insulating film is 1 nm to 120 nm. Is 1 nm to 10 nm, more preferably 1.5 nm to 6 nm, and even more preferably 1.5 nm to 3 nm.
(2. Action)
The operation of insulating film deposition in the AlGaN / GaN heterostructure FET of the present invention will be described.
FIG. 2 shows Al with a thickness of 8 to 20 nm. _0.4 Ga _0.6 Al with N barrier layer _0.4 Ga _0.6 In the N / GaN heterostructure FET, the dependence of the electron mobility, two-dimensional electron concentration, channel sheet resistance on the AlGaN barrier layer thickness is plotted for the SiN insulating film 30 nm deposited on the AlGaN surface and the non-deposited one. Is. FIG. 2A is a graph showing electron mobility. In FIG. 2A, a black symbol indicates that the SiN insulating film is not deposited, and a hollow symbol indicates that the SiN insulating film is deposited to 30 nm. It can be seen that when the SiN insulating film is deposited on the AlGaN surface, the mobility is slightly reduced as compared with the case where the SiN insulating film is not deposited. However, when the SiN insulating film is deposited on the AlGaN surface, the mobility when the thickness of the AlGaN barrier layer changes from 8 nm to 20 nm is 640 cm. ² / Vs ~ 700cm ² / Vs is almost constant, and the variation is small.
FIG. 2B is a graph showing the two-dimensional electron concentration. In FIG. 2B, a black symbol indicates that no SiN insulating film is deposited, and a hollow symbol indicates that a SiN insulating film is deposited by 30 nm. From FIG. 2B, it can be seen that the two-dimensional electron concentration is significantly increased in the case where the SiN insulating film is deposited on the AlGaN surface compared to the case where the SiN insulating film is not deposited. When the SiN insulating film is deposited on the AlGaN surface, the secondary electron concentration value when the film thickness of the AlGaN barrier layer changes from 8 nm to 20 nm is 2.6 × 10 6. ¹³ cm ^-2 ~ 3.2 × 10 ¹³ cm ^-2 It can be seen that there is little variation between the two. It can also be seen that the thinner the AlGaN barrier layer, the more significant the difference in two-dimensional electron concentration depending on whether or not there is a SiN insulating film.
FIG. 2C is a graph showing channel sheet resistance. In FIG. 2C, a black symbol indicates that the SiN insulating film is not deposited, and a hollow symbol indicates that the SiN insulating film is deposited to 30 nm. The channel sheet resistance shown in FIG. 2C is inversely proportional to the product of mobility and two-dimensional electron concentration. For this reason, when there is a SiN insulating film, the resistance of the channel is lower than when there is no SiN insulating film. It can also be seen that the effect is more prominent when the AlGaN barrier layer is thin. As a result, the sheet resistance increases monotonically as the AlGaN film thickness decreases, while the SiN insulating film does not increase, while the SiN insulating film does not increase substantially. .
FIG. 3 shows an Al film thickness of 4 to 10 nm. _0.4 Ga _0.6 Al with N barrier layer _0.4 Ga _0.6 In the N / GaN heterostructure FET, the dependence of the electron mobility, two-dimensional electron concentration, channel sheet resistance on the AlGaN barrier layer thickness was plotted for the SiN insulating film 2 nm deposited on the AlGaN surface and the non-deposited one. Is. 3A shows the electron mobility, FIG. 3B shows the two-dimensional electron concentration, and FIG. 3C shows the channel sheet resistance. In FIG. 3, a black symbol indicates that no SiN insulating film is deposited, and a hollow symbol indicates that a SiN insulating film is deposited by 2 nm.
FIG. 3A is a graph showing electron mobility. The SiN insulating film deposited on the AlGaN surface has a mobility of 670 cm when the thickness of the AlGaN barrier layer changes from 4 nm to 10 nm. ² / Vs ~ 740cm ² / Vs is almost constant, and the variation is small.
FIG. 3B is a graph showing the two-dimensional electron concentration. It can be seen from FIG. 3B that the two-dimensional electron concentration is significantly increased when the SiN insulating film is deposited on the AlGaN surface as compared with the case where the SiN insulating film is not deposited. In the case where the SiN insulating film is deposited on the AlGaN surface, the value of the secondary electron concentration when the thickness of the AlGaN barrier layer changes from 4 nm to 10 nm is 2 × 10. ¹³ cm ^-2 ~ 3x10 ¹³ cm ^-2 It can be seen that there is little variation between the two. It can also be seen that the thinner the AlGaN barrier layer, the more significant the difference in two-dimensional electron concentration depending on whether or not there is a SiN insulating film.
FIG. 3C is a graph showing channel sheet resistance. From FIG. 3 (c), when the SiN insulating film is deposited on the AlGaN surface, the channel sheet resistance is lower than that when the SiN insulating film is not deposited, and takes a substantially constant value even when the film thickness of the AlGaN barrier layer changes. I understand.
From FIG. 3, as in the case of the SiN insulating film 30 nm shown in FIG. 2, when the SiN insulating film 2 nm is deposited on the AlGaN surface, the two-dimensional electron concentration is greatly increased as compared with the case where the SiN insulating film is not deposited. It can be seen that the sheet resistance is greatly reduced. Further, the thinner the AlGaN barrier layer, the more conspicuous the difference in two-dimensional electron concentration depending on whether or not there is a SiN insulating film.
These results are because the high-density surface states represented by fixed charges existing on the AlGaN surface are almost neutralized by depositing the SiN insulating film, and the density of the surface states is greatly reduced. It is believed that there is. When the film thickness of the AlGaN barrier layer is thin, the effect of the electric field that generates the surface states (in this case, it works in the direction of decreasing the electron density of the channel) is large, and therefore there is a case where the SiN insulating film is present and not present It is thought that the difference of
Reducing the thickness of the AlGaN barrier layer leads to improved gate effectiveness and increased mutual conductance. However, in the case of an ordinary AlGaN / GaN heterostructure, there is a problem that the channel two-dimensional electron gas concentration is reduced by reducing the thickness, resulting in an increase in channel resistance. However, by neutralizing the surface state by depositing the insulating film of the present invention, the AlGaN barrier layer can be thinned without reducing the two-dimensional electron concentration. This can reduce the overall resistance of the AlGaN / GaN heterostructure FET, leading to an increase in current, power output and transconductance.
FIG. 4 shows an 8 nm thick Al film. _0.4 Ga _0.6 Al with N barrier layer _0.4 Ga _0.6 Electron mobility, two-dimensional electron concentration, channel of N / GaN heterostructure FET of SiN insulating film not deposited on AlGaN surface, 2 nm deposited, and further deposited 120 nm (total 122 nm deposited) The sheet resistance is plotted. As can be seen from FIG. 4, there is a large two-dimensional electron concentration increase and a decrease in sheet resistance between those not deposited and those deposited SiN 2 nm, but there is a large difference between SiN 2 nm and SiN 122 nm. Absent. From this, it can be seen that the large increase in the two-dimensional electron concentration due to the SiN deposition is basically an effect only by covering the surface with SiN regardless of the SiN film thickness.
FIG. 5 shows Al with a film thickness of 6 nm. _0.4 Ga _0.6 Al with N barrier layer _0.4 Ga _0.6 In the N / GaN heterostructure FET, where the SiN insulating film is not deposited on the AlGaN surface, the electron mobility, the two-dimensional electron concentration, and the location dependence on the channel sheet resistance of the one deposited by 2 nm are plotted. 5A shows the electron mobility, FIG. 5B shows the two-dimensional electron concentration, and FIG. 5C shows the channel sheet resistance. The position on the horizontal axis represents the distance of the measured point from the center of the 2-inch wafer. That is, as the numerical value increases, the measurement position moves from the center to the substrate edge. In FIG. 5, black symbols indicate that the SiN insulating film is not deposited, and hollow symbols indicate that the SiN insulating film is deposited to 2 nm. As can be seen from FIGS. 5A to 5C, in the case where the SiN insulating film is not deposited on the AlGaN surface, the mobility varies depending on the position on the wafer. This indicates that because the AlGaN barrier layer surface is very close to the channel, the difference in AlGaN surface state density due to slight differences in growth conditions has a significant effect on the electron mobility in the channel. Yes. However, by depositing 2 nm of the SiN insulating film, as described above, the high-density surface level represented by the fixed charges existing on the AlGaN surface is almost neutralized, and the density of the surface level is greatly reduced. At the same time, there is no difference in electron density depending on the location on the wafer, and uniform electron mobility within the wafer surface is obtained. As a result, the in-plane uniformity of the sheet resistance is considered to be greatly improved.
That is, as described above, the SiN insulating film has an effect on the mobility, the electron concentration and the like even if the film thickness is small. As shown in FIG. Deposited on the AlGaN surface has an electron mobility of 730 cm on the wafer. ² / Vs ~ 750cm ² / Vs is almost constant, and the change in electron mobility in a range of 20 mm from a specific position (the ratio of the difference between the maximum value and the minimum value of electron mobility when the maximum value of electron mobility is 100%) 10% or less (preferably 5% or less).
FIG. 5B is a graph showing the two-dimensional electron concentration. From FIG. 5 (b), it can be seen that the two-dimensional electron concentration in the case where the SiN insulating film is deposited on the AlGaN surface is significantly increased as compared with the case where it is not deposited. In the case where the SiN insulating film is deposited on the AlGaN surface, the two-dimensional electron concentration on the wafer is 2.25 × 10 6. ¹³ cm ^-2 ~ 2.35x10 ¹³ cm ^-2 Change of the two-dimensional electron concentration in a range of 20 mm from a specific position (the difference between the maximum value and the minimum value of the two-dimensional electron concentration when the maximum value of the two-dimensional electron concentration is 100%) Ratio) is 10% or less (preferably 5% or less).
FIG. 5C is a graph showing channel sheet resistance. From FIG. 5 (c), when the SiN insulating film is deposited on the AlGaN surface, the channel sheet resistance is lower than that when the SiN insulating film is not deposited, and a substantially constant value (specifically, even if the film thickness of the AlGaN barrier layer changes). It can be seen that 360 Ω / □ to 370 Ω / □ is taken. More specifically, the change in sheet resistance in a range of 20 mm from a specific position (the ratio of the difference between the maximum value and the minimum value of sheet resistance when the maximum value of sheet resistance is 100%) is 10% or less (5 % Or less).
(3. Manufacturing method)
The heterojunction FET of the present invention grows crystals by a known method such as RF plasma molecular beam epitaxy growth method (RF-MBE), gas source molecular beam epitaxy growth method using ammonia gas, metal organic vapor phase growth method, Each layer can be formed and manufactured by depositing crystals. For example, in the crystal growth method of the AlGaN / GaN heterojunction FET structure by the RF-MBE method, in the case of GaN, a gallium molecule evaporated from a gallium source heated in a Knudsen cell by heating a substrate placed in an ultra-high vacuum growth chamber. And nitrogen gas (N ₂ ) Can be grown on the substrate simultaneously with the nitrogen radical molecular beam obtained by decomposing the). In the case of growing AlGaN, it can be manufactured by supplying an aluminum molecular beam to the substrate at the same time (see, for example, JP-A-2003-192497). In addition, for example, a heterojunction FET may be manufactured according to the methods described in JP2003-258005A and JP2003-243424A. Hereinafter, a method of manufacturing the heterojunction FET structure of the present invention will be described with reference to the drawings.
FIG. 6 is a diagram illustrating a schematic configuration of an RF-MBE apparatus used in the RF-MBE method. In the RF-MBE apparatus, a heating unit 12 is provided in a growth chamber 11 that can realize an ultrahigh vacuum by a vacuum pump (not shown), and the sapphire substrate 13 is heated by this heating unit. Further, an Al cell 14a, a Ga cell 14b, an In cell 14c, and an RF plasma cell 14d for irradiating a molecular beam onto the sapphire substrate 13 are provided and can be opened and closed by a shutter 15, respectively. FIG. 6 shows an example in which the shutters of the Al cell 14a and the RF plasma cell 14d are opened.
Below, the example which manufactures the laminated body shown in FIG. 1 using the RF-MBE apparatus shown in FIG. 6 is demonstrated. First, the sapphire substrate 13 is washed using an organic solvent. Further, a high melting point metal is vacuum-deposited on the back surface of the sapphire substrate 13 in order to improve the temperature rise. The sapphire substrate 13 is placed with the back surface facing the heating means 12 in the growth chamber 11, and is heated to about 800 ° C. or higher by the heating means 12 to perform high-temperature cleaning of the substrate surface of the sapphire substrate 13.
Next, the temperature of the substrate is lowered to about 300 ° C., and the high-purity nitrogen gas is decomposed in the RF plasma cell 14d. By supplying the nitrogen radical molecular beam thus obtained onto the sapphire substrate 13 and nitriding the surface of the sapphire substrate, a thin aluminum nitride layer is formed on the surface. The plasma output is 100 W to 700 W, preferably 200 W to 600 W. The flow rate of the nitrogen gas is 0.1 sccm to 2.0 sccm, preferably 0.3 sccm to 1.5 sccm, more preferably 0.5 sccm to 1.2 sccm.
Next, the temperature of the sapphire substrate 13 is raised to, for example, 900 ° C. by the heating means 12. And an aluminum molecular beam is obtained by heating in a Knudsen cell. An aluminum molecular beam and a nitrogen radical molecular beam generated by RF plasma are simultaneously supplied onto the sapphire substrate 13. Thereby, an AlN buffer layer is grown.
Here, examples of the growth temperature of the AlN buffer layer include 700 ° C. or higher, but a preferable temperature range is 800 ° C. to 900 ° C. When the temperature is 700 ° C. or higher, growth of AlN AlN is realized, and an AlN layer and a GaN layer grown thereon are excellent in crystallinity compared to N polarity. Further, when the temperature is 600 ° C. or lower, the polarity of the AlN buffer layer tends to be N polarity.
Next, the shutter 15 of the Al cell 14a is closed and the shutter 15 of the Ga cell 14b is opened. Thereby, a gallium molecular beam and a nitrogen radical molecular beam are simultaneously supplied onto the sapphire substrate 13 to grow a GaN layer on the AlN buffer layer.
Here, the growth temperature of the GaN layer may be 650 ° C. or higher, but a preferable temperature range is 700 ° C. to 800 ° C. When the temperature is 800 ° C. or higher, the amount of reevaporation without being incorporated into the Ga molecular beam crystal in the growth of GaN becomes extremely large, the growth rate is extremely reduced, and when the temperature is 700 ° C. or lower, the crystallinity of the GaN layer. This is because it becomes bad.
As described above, after the GaN layer has grown to the required thickness, the shutter 15 of the Al cell 14a is opened while the Ga cell 14b and the nitrogen radical shutter 15 remain open. Thereby, an AlGaN layer is grown.
Note that an AlN spacer layer may be formed before the AlGaN layer is formed.
Here, the growth temperature of the AlGaN layer is the same conditions as in the case of GaN, and the preferred temperature range is 700 ° C. to 800 ° C. When the temperature is 800 ° C. or higher, the amount of reevaporation without being taken into the crystal of the Ga molecular beam in the growth of GaN becomes very large, the growth rate is extremely lowered, and it becomes difficult to match the composition ratio of AlGaN. This is because the crystallinity of the AlGaN layer is not good when the temperature is not higher than ° C.
Examples of the growth rate of the AlGaN layer include 1 nm / hour to 5000 nm / hour, preferably 10 nm / hour to 2000 nm / hour, more preferably 50 nm / hour to 1000 nm / hour, and further preferably 100 nm / hour. It is -800 nm / hour, Especially preferably, it is 300 nm / hour-700 nm / hour. This is because it is difficult to obtain a crystal having excellent crystallinity even if the crystal growth rate is too fast or too slow.
Next, electrodes (source, gate, drain electrode) are formed by a known means.
After forming the electrode, an insulating film is deposited. The insulating film is, for example, SiN, SiO ₂ , SiON, Al ₂ O ₃ Alternatively, it may be formed by a CVD (Chemical Vapor Deposition) method using a raw material made of any one or more of AlN. Examples of the CVD method used for forming the insulating film include a thermal CVD method, an ECR-CVD method, a VHF-CVD method, and a hot wire CVD method, and among these, the hot wire CVD method is preferable. The hot wire CVD method (hot wire-CVD) is a method that utilizes the catalytic effect of the tungsten surface heated to a high temperature, and is also called catalytic CVD method (catalytic-CVD) or hot filament CVD method (hot filament CVD). Yes.
Hot wire CVD methods are disclosed in, for example, Japanese Patent Application Laid-Open Nos. 2004-27326, 1704110, 3145536, 2000-277501, 2000-277502, 2004-35981, and 2004-91802. , JP-A-2004-91821, JP-A-2004-99917, and JP-A-2004-103745 may be appropriately used.
For example, as a source gas for forming the SiN insulating film, a silicon source gas is a compound composed of hydrogen, nitrogen, or a halogen element, such as SiH. ₄ , Si ₂ H ₆ , Si ₃ H ₈ , SiF ₄ , SiCl ₄ , SiCl ₂ H ₂ Any one or more of the above, and the nitrogen source gas may be NH ₃ , N ₂ One or both of O (see JP-A-5-095120 and JP-A-2000-208417) can be mentioned, and a preferable silicon source gas is SiH ₄ The preferred nitrogen source gas is NH ₃ It is.
H for dilution gas ₂ , N ₂ , He, Ar, Ne, or Xe may be used.
In film formation, these gases are adjusted to a desired flow rate and mixing ratio using a pressure reducing valve, a mass flow controller, etc., introduced into the reaction chamber, and through a number of gas passage holes formed in the outer peripheral wall of the cassette body, Supply to heating element. As the heating element, a refractory metal such as tungsten is generally used.
The gas pressure at the time of film formation may be set to 0.1 to 100 Pa, preferably 1.0 to 10 Pa, more preferably 3 to 7 Pa. By setting the gas pressure within this range, the supplied gas is reduced. Efficiently decomposed and transported. Moreover, the secondary reaction in the gas phase between reaction products is suppressed, and as a result, a high-quality insulating film can be formed on the substrate.
Here, examples of the substrate temperature during the deposition of the insulating film include 150 ° C. to 800 ° C., preferably 200 ° C. to 500 ° C., more preferably 200 ° C. to 400 ° C., 250 ° C. to 500 ° C., 300 ° C. to 500 ° C. 300-450 ° C or 350-400 ° C. The deposition rate of the insulating film is 0.1 nm / hour to 5000 nm / hour, preferably 1 nm / hour to 100 nm / hour, more preferably 1 nm / hour to 50 nm / hour, and still more preferably 1 nm / hour. Time to 30 nm / hour, particularly preferably 1 nm / hour to 20 nm / hour.
Note that as a method for measuring the substrate temperature during deposition in this specification, a method in which the temperature is measured with a thermocouple may be employed. In the hot wire CVD, the temperature may be measured by a thermocouple attached to the substrate holder.
The thickness of each layer can be adjusted by controlling the deposition time. You may observe and photograph with TEM (transmission electron microscope), and may measure thickness from the cross-sectional photograph. Examples of the TEM apparatus include a transmission electron microscope (H-7100FA type manufactured by Hitachi, Ltd.). In order to measure the thickness and refractive index of the insulating film, a known device such as an ellipsometer may be used.

Hereinafter, an example in which an AlGaN / GaN heterojunction FET is manufactured on a sapphire substrate by the above-described GaN compound semiconductor lamination method will be described.
The sapphire substrate is cleaned with an organic solvent, and the sapphire substrate having a high melting point metal titanium vapor-deposited on the back surface is improved to an ultrahigh vacuum (for example, 10 ⁻¹¹ Torr to ^{10 −10} Torr). It was installed on the substrate heater in the MBE growth chamber that was kept. Then, the temperature of the substrate was raised to about 800 ° C. and held for 30 minutes as it was to clean the surface of the sapphire substrate at a high temperature. Thereafter, the substrate temperature was lowered to 300 ° C. Subsequently, nitrogen radicals obtained by decomposing nitrogen gas with RF plasma were irradiated. As a result, the surface of the sapphire substrate was nitrided for 60 minutes, and thin aluminum nitride was formed on the surface.
While the shutter 15 of the RF plasma cell 14d was opened, the substrate temperature was raised to 900 ° C. without interrupting irradiation of nitrogen radicals on the substrate surface. Thereafter, the shutter of the Al cell 14a was opened, and the AlN buffer layer was grown to a film thickness of 300 nm. The substrate temperature was lowered to 730 ° C. Thereafter, the shutter of the Al cell 14a was closed and simultaneously the shutter of the Ga cell 14b was opened, and a GaN layer was grown at a substrate temperature of 730 ° C. until the film thickness reached 1500 nm.
After the growth of the GaN layer was completed, the shutter of the Ga cell 14b was closed and simultaneously the shutter of the Al cell 14a was opened, and the AlN layer was grown to a thickness of 1.3 nm. Thereafter, the shutter of the Ga cell 14b was opened, and the AlGaN layer was grown to a thickness of 8 nm.
Thus, after obtaining the semiconductor laminated body, the electrode was formed. Insulation with adjacent transistors was obtained by reactive gas etching up to the GaN layer. Next, a metal multilayer film composed of Ti / Al / Ni / Au is vacuum-deposited on the AlGaN barrier layer and heated using an infrared lamp to obtain an ohmic junction between the semiconductor layer and the metal. An electrode and a drain electrode were prepared. The distance between the source and drain electrodes was 5 μm. Finally, Ni / Au was vacuum-deposited on the AlGaN barrier layer to obtain a Schottky junction, thereby producing a gate electrode having a length of 1 μm and a width (depth) of 50 μm.
After completion of the electrode formation process, a 30 nm-thickness SiN insulating film was deposited on the transistor surface by hot wire CVD. Then, SiN was etched and punched by performing reactive gas etching on the electrode metal pad portion for probing so that the metal probe could be contacted during device characteristic measurement.
The transistor thus manufactured had a maximum current density of 590 mA / mm and a maximum transconductance of 291 mS / mm.
Comparative Example 1
A heterojunction FET was manufactured in the same process as in Example 1 except that no SiN deposition was performed. This heterojunction FET had a maximum current density of 425 mA / mm and a maximum transconductance of 229 mS / mm.

A heterojunction FET was manufactured by the same process as in Example 1 except that the AlGaN film thickness was 18 nm. This heterojunction FET had a maximum current density of 725 mA / mm and a maximum transconductance of 190 mS / mm.
Comparative Example 2
A heterojunction FET was manufactured in the same process as in Example 2 except that no SiN deposition was performed. This heterojunction FET had a maximum current density of 660 mA / mm and a maximum transconductance of 160 mS / mm.
From Example 1 and Comparative Example 1, and Example 2 and Comparative Example 2, it can be seen that the thinner the barrier layer, the better the current density and mutual conductance characteristics due to the effect of the insulating film.

  The AlGaN film thickness is 10 nm, and the process up to the fabrication of the source and drain electrodes is the same as in Example 1. Thereafter, a 2 nm SiN insulating film is deposited, and a gate electrode that is further miniaturized using electron beam exposure is fabricated on the SiN insulating film. A heterojunction FET was manufactured. From Example 1, the gate electrode metal was changed from Ni / Au to Ti / Pt / Au, the source / drain electrode interval was changed from 5 μm to 2 μm, the gate length was changed from 1 μm to 0.06 μm, and the gate width was changed from 50 μm to 100 μm. Yes. In Example 3, the gate electrode is formed on the AlGaN barrier layer in Example 1, whereas the gate electrode metal is deposited and formed on the SiN insulating film, as shown in FIG. It is a heterojunction FET with a MIS structure. This heterojunction FET had a maximum current density of 1.55 A / mm, a maximum transconductance of 340 mS / mm, a current gain cutoff frequency of 152 GHz, and a maximum oscillation frequency of 173 GHz.

  A heterojunction FET was prepared in the same manner as in Example 3 except that the AlGaN film thickness was 8 nm. This heterojunction FET had a maximum current density of 1.25 A / mm, a maximum transconductance of 305 mS / mm, a current gain cutoff frequency of 163 GHz, and a maximum oscillation frequency of 184 GHz.

  A heterojunction FET was prepared in the same manner as in Example 3 except that the AlGaN film thickness was 6 nm. This heterojunction FET had a maximum current density of 1.2 A / mm, a maximum transconductance of 336 mS / mm, a current gain cutoff frequency of 153 GHz, and a maximum oscillation frequency of 182 GHz.

  A heterojunction FET was prepared in the same manner as in Example 3 except that the AlGaN film thickness was 4 nm. This heterojunction FET had a maximum current density of 1.05 A / mm, a maximum transconductance of 391 mS / mm, a current gain cutoff frequency of 127 GHz, and a maximum oscillation frequency of 188 GHz.

The heterojunction FET of the present invention can be used as an FET that can cope with high speed and high frequency.
The heterojunction FET of the present invention can be used as an element used in a vehicle-mounted collision avoidance radar, an intelligent road traffic system (ITS), a vehicle wireless device for vehicle-to-vehicle communication, and the like.
The heterojunction FET of the present invention operates stably even at high temperatures and is not easily deteriorated by radiation, so that it can be used effectively in outer space. Therefore, the heterojunction FET of the present invention can be used as an electronic device used in outer space such as an artificial satellite or a planetary probe.

Claims (24)

A GaN-based field effect transistor having a heterostructure including a channel layer and a barrier layer, wherein the field effect transistor has an insulating film on the surface of the transistor element. The field effect transistor according to claim 1, wherein the insulating film is an insulating film made of any one of SiN, SiO ₂ , SiON, Al ₂ O ₃ , and AlN. 2. The field effect transistor according to claim 1, wherein the insulating film is an insulating film made of SiN formed by a hot wire CVD method. The field effect transistor according to claim 1, wherein a change in electron mobility in a range of 20 mm from a specific position of the field effect transistor is 10% or less. The field effect transistor according to claim 1, wherein a change in secondary electron concentration in a range of 20 mm from a specific position of the field effect transistor is 10% or less. The field effect transistor according to claim 1, wherein the insulating film has a thickness of 1 nm to 1 μm. 2. The field effect transistor according to claim 1, wherein the insulating film is made of SiN formed by a hot wire CVD method, and the thickness of the insulating film is 1 nm to 100 nm. The field effect transistor according to claim 1, wherein the channel layer is made of GaN and the barrier layer is made of AlGaN. The field effect transistor according to claim 1, wherein the barrier layer has a thickness of 1 to 30 nm. The field effect transistor according to claim 1, wherein the barrier layer has a thickness of 3 to 20 nm. The field effect transistor according to claim 1, wherein the barrier layer has a thickness of 5 to 15 nm. The field effect transistor according to claim 1, wherein the channel layer has a thickness of 100 nm to 10 μm. A field effect transistor in which a buffer layer, a channel layer made of GaN, and a barrier layer made of AlGaN are formed in this order on a substrate, the thickness of the barrier layer being 1 to 30 nm, and an insulating film on the surface of the transistor element Heterojunction field effect transistor. The field effect transistor according to claim 13, wherein the insulating film is an insulating film made of any one of SiN, SiO ₂ , SiON, Al ₂ O ₃ , and AlN. 14. The field effect transistor according to claim 13, wherein the insulating film is an insulating film made of SiN formed by a hot wire CVD method. The field effect transistor according to claim 13, wherein the change in electron mobility in a range of 20 mm from a specific position of the field effect transistor is 10% or less. The field effect transistor according to claim 13, wherein the change in secondary electron concentration in a range of 20 mm from a specific position of the field effect transistor is 10% or less. The field effect transistor according to claim 13, wherein the insulating film has a thickness of 1 nm to 1 μm. The field effect transistor according to claim 13, wherein the insulating film is made of SiN formed by a hot wire CVD method, and the thickness of the insulating film is 1 nm to 100 nm. The field effect transistor according to claim 13, wherein a spacer layer is provided between the channel layer and the barrier layer. Forming a buffer layer, a channel layer made of GaN, and a barrier layer made of AlGaN in this order on the substrate;
Forming a source electrode, a gate electrode, and a drain electrode;
Forming an insulating film on the surface of the barrier layer;
For producing a field effect transistor having a heterostructure including: Forming an insulating film on the surface of the barrier layer,
_{SiN, SiO 2, SiON, Al} 2 O 3, or any of AlN as a raw material, a method of manufacturing a field effect transistor having a heterostructure according to claim 21 wherein forming the insulating film by the hot wire CVD. The method of manufacturing a field effect transistor having a heterostructure according to claim 21, wherein the insulating film has a thickness of 1 nm to 1 µm. The method for producing a field effect transistor having a heterostructure according to claim 21, wherein the barrier layer made of AlGaN has a thickness of 3 nm to 20 nm.

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