JPWO1996042112A1 - Semiconductor integrated circuit device, its manufacturing method, and semiconductor wafer - Google Patents

Abstract

(57) [Abstract] A semiconductor integrated circuit device using an SOI substrate has p-channel MISFETs Qp and n-channel MISFETs Qn formed on the main surfaces of semiconductor layers 3a and 3b formed on a semiconductor substrate 1 (n-type well 4) with an insulating layer 2 interposed therebetween, and openings 5 are provided in the insulating layer 2 below the channel regions of each of the p-channel MISFETs Qp and n-channel MISFETs Qn, and the channel regions and the semiconductor substrate 1 (n-type well 4) are electrically connected through these openings 5.

Description

[Detailed Description of the Invention] Semiconductor Integrated Circuit Device, Its Manufacturing Method, and Semiconductor Wafer Technical Field The present invention relates to semiconductor integrated circuit devices and their manufacturing techniques, particularly to techniques that are effective when applied to semiconductor integrated circuit devices with an SOI (Silicon-On-Insulator) structure.

BACKGROUND ART SOI technology, which forms a thin semiconductor layer on a semiconductor substrate via an insulating layer and then fabricates devices in this semiconductor layer, allows for complete device isolation, offering the following advantages over fabricating semiconductor devices on a single-crystal silicon substrate:

(1) Parasitic capacitance between wiring and the substrate and diffusion layer capacitance are reduced, which enables the operating speed of LSIs to be improved.

(2) Since the generation of electron-hole pairs by alpha rays is limited to a thin semiconductor layer, soft error resistance is high, which is advantageous for miniaturization of memory elements.

(3) Active parasitic effects such as parasitic bipolar transistors are reduced, making it possible to form latch-up-free complementary MISFETs.

However, a problem with SOI technology is that the threshold voltage of the MISFET formed in the semiconductor layer is prone to fluctuation.

For example, IEEE Transactions on Electron Devices, Vol. 38, No. 6, June 1991, pp. 1384-1391, "Analysis and Control of Floating-Body Bipolar Effects in Fully Depleted Submicrometer SOI MOSFETs," reports that when the channel region of a MISFET formed on an SOI substrate is surrounded by the source and drain regions and insulated from the substrate, causing a floating state, a kink occurs in the gate voltage-drain current characteristic, resulting in a shift in the threshold voltage.

Therefore, to ensure stable operation of MISFETs formed on SOI substrates, it is necessary to create a structure that prevents the MISFET channel region from being in a floating state.

For example, the aforementioned literature discloses a technique for preventing floating of the channel region by forming the semiconductor layer thin enough to completely deplete the channel region when a gate voltage is applied.

Furthermore, Japanese Patent Laid-Open Publication No. 62-109355 discloses a technique for preventing floating of a channel region by forming a second p-type semiconductor region electrically connected to a p-type semiconductor region in which a channel region is formed at the end of the source/drain region (n-type semiconductor region) of an n-channel MISFET and applying a fixed potential to this second p-type semiconductor region.

However, in the first conventional technique, in which the semiconductor layer is formed thin enough that the channel region is completely depleted when a gate voltage is applied, (1) the resistance of the source and drain regions formed in the semiconductor layer increases, resistance of the MISFET decreases.

(2) The parasitic bipolar transistor effect becomes apparent, which reduces the threshold voltage and makes it difficult to obtain an enhancement-mode MISFET.

Problems such as the following arise.

Furthermore, in the case of the second conventional technology in which p-type semiconductor regions for supplying a fixed potential are formed at the ends of the source and drain regions (n-type semiconductor regions) of an n-channel MISFET, (1) the provision of these p-type semiconductor regions reduces the effective gate width of the MISFET, resulting in a reduction in current drive capability.

(2) The junction capacitance of the source and drain regions increases, reducing the operating speed of the MISFET.

Problems such as the following arise.

The object of the present invention is to provide a technology that can prevent fluctuations in the threshold voltage of a MISFET formed on an SOI substrate and set the threshold voltage to an enhancement type.

Another object of the present invention is to provide a technique that can prevent fluctuations in the threshold voltage of a MISFET formed on an SOI substrate and improve the current drive capability.

The above and other objects and novel features of the present invention will become apparent from the description in the specification and the accompanying drawings.

DISCLOSURE OF THE INVENTION In a semiconductor integrated circuit device with an SOI structure according to the present invention, a MISFET is formed on the principal surface of a semiconductor layer formed on a semiconductor substrate via an insulating layer. An opening is provided in the insulating layer below the channel region of the MISFET, and the channel region and the semiconductor substrate are electrically connected through the opening.

A method for manufacturing a semiconductor integrated circuit device according to the present invention includes the steps of: (a) forming an insulating layer on a semiconductor substrate, and then etching the insulating layer to form a plurality of openings at predetermined intervals that reach the semiconductor substrate; (b) epitaxially growing a semiconductor layer on the semiconductor substrate exposed at the bottom of each opening, thereby covering the entire upper surface of the insulating layer; (c) thinning the semiconductor layer to a predetermined thickness, and then forming an insulating film for element isolation on a major surface of the semiconductor layer; and (d) forming a MISFET on the major surface of the semiconductor layer, with a channel region partially disposed above the opening.

According to the above-described configuration, the channel region of the MISFET is electrically connected to the semiconductor substrate through the opening in the insulating layer, thereby preventing fluctuations in the threshold voltage due to the floating of the channel region, thereby ensuring stable operation of the MISFET.

Furthermore, since the threshold voltage can be controlled without thinning the semiconductor layer to the point where the channel region is completely depleted when a gate voltage is applied, an increase in the resistance of the source and drain regions can be prevented, improving the current drive capability of the MISFET. Furthermore, a decrease in threshold voltage due to the manifestation of the parasitic bipolar transistor effect can be prevented, and the threshold voltage of the MISFET can be set to an enhancement type.

Furthermore, a fixed potential can be supplied to the channel region through an opening in the insulating layer below the semiconductor layer, preventing a reduction in the effective gate width and improving the current drive capability of the MISFET. Furthermore, an increase in the junction capacitance of the source and drain regions can be prevented, improving the operating speed of the MISFET.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a plan view of a portion of an SOI substrate illustrating a semiconductor integrated circuit device according to a first embodiment of the present invention. FIG. 2 is a cross-sectional view taken along line II-II' in FIG. 1. FIG. 3 is a cross-sectional view of a portion of an SOI substrate illustrating a method for manufacturing a semiconductor integrated circuit device according to a first embodiment of the present invention. FIG. 4 is a cross-sectional view of a portion of an SOI substrate illustrating a method for manufacturing a semiconductor integrated circuit device according to a first embodiment of the present invention. FIG. 5 is a cross-sectional view of a portion of an SOI substrate illustrating a method for manufacturing a semiconductor integrated circuit device according to a first embodiment of the present invention. FIG. 6 is a perspective view of an SOI substrate illustrating a method for manufacturing a semiconductor integrated circuit device according to a first embodiment of the present invention. FIG. 7 is a cross-sectional view of a portion of an SOI substrate illustrating a method for manufacturing a semiconductor integrated circuit device according to a first embodiment of the present invention. FIG. 8 is a cross-sectional view of a portion of an SOI substrate illustrating a method for manufacturing a semiconductor integrated circuit device according to a first embodiment of the present invention. FIG. 9 is a cross-sectional view of a portion of an SOI substrate illustrating a method for manufacturing a semiconductor integrated circuit device according to a first embodiment of the present invention. FIG. 10 is a cross-sectional view of a key portion of an SOI substrate illustrating a method for manufacturing a semiconductor integrated circuit device according to a first embodiment of the present invention; FIG. 11 is a cross-sectional view of a key portion of an SOI substrate illustrating a method for manufacturing a semiconductor integrated circuit device according to a first embodiment of the present invention; FIG. 12 is a cross-sectional view of a key portion of an SOI substrate illustrating a method for manufacturing a semiconductor integrated circuit device according to a first embodiment of the present invention; FIG. 13 is a cross-sectional view of a key portion of an SOI substrate illustrating a method for manufacturing a semiconductor integrated circuit device according to a second embodiment of the present invention; FIG. 14 is a cross-sectional view of a key portion of an SOI substrate illustrating a method for manufacturing a semiconductor integrated circuit device according to a second embodiment of the present invention; FIG. 15 is a cross-sectional view of a key portion of an SOI substrate illustrating a method for manufacturing a semiconductor integrated circuit device according to a second embodiment of the present invention; FIG. 16 is a cross-sectional view of a key portion of an SOI substrate illustrating a method for manufacturing a semiconductor integrated circuit device according to a second embodiment of the present invention; and FIG. 17 is a cross-sectional view of a key portion of an SOI substrate illustrating a method for manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention.

BEST MODE FOR CARRYING OUT THE INVENTION To explain the present invention in more detail, the present invention will be described with reference to the accompanying drawings. Note that throughout the drawings illustrating the embodiments, components having the same functions are designated by the same reference numerals, and repeated explanations will be omitted.

(First Embodiment) A semiconductor integrated circuit device according to a first embodiment of the present invention is shown in Figures 1 and 2. Figure 1 is a plan view of the essential parts of an SOI substrate, and Figure 2 is a cross-sectional view taken along line II-II' in Figure 1.

The semiconductor integrated circuit device of this embodiment has a CMOS (Complimentary MOS) circuit formed on the main surface of an SOI substrate that includes a semiconductor substrate 1 and semiconductor layers 3a and 3b formed on the semiconductor substrate 1 with an insulating layer 2 interposed therebetween, and the CMOS circuit is formed of an n-channel MISFET Qn and a p-channel MISFET Qp.

The semiconductor substrate 1 is made of p-type single crystal silicon (Si), and has an n-type well 4 formed in a part thereof. The insulating layer 2 is composed of a silicon oxide layer in which a large number of openings 5 are formed at equal intervals. The semiconductor layer 3a is made of n ^- type epitaxial single crystal silicon, and is electrically connected to the n-type well 4 through the openings 5 formed in the insulating layer 2 below it. The semiconductor layer 3b is made of p ^- type epitaxial single crystal silicon, and is electrically connected to the p-type semiconductor substrate 1 through the openings 5 formed in the insulating layer 2 below it.

The n-channel MISFET Qn is formed on the main surface of the active region of the p ^- type semiconductor layer 3b surrounded by a field insulating film 6 for element isolation made of silicon oxide. The n-channel MISFET Qn is composed of an n-type semiconductor region (source region, drain region) 7 formed in the semiconductor layer 3b, a gate insulating film 8 made of silicon oxide formed on the surface of the semiconductor layer 3b, and a gate electrode 9 made of polycrystalline silicon formed on the gate insulating film 8. The semiconductor layer 3b directly below this gate electrode 9, i.e., the channel region, is electrically connected to the semiconductor substrate 1 through the opening 5 in the insulating layer 2.

To another active region of the p ⁻ type semiconductor layer 3 b, a wiring 12 is connected through a connection hole 11 formed in a silicon oxide insulating film 10, and a substrate potential of about −2 V is supplied. This semiconductor layer 3 b is electrically connected to the semiconductor substrate 1 through an opening 5 in the insulating layer 2 below it, similar to the semiconductor layer 3 b in which the n channel type MISFET Qn is formed.

In this way, the channel region of the n-channel MISFET Qn is electrically connected to the semiconductor substrate 1 through the opening 5 in the insulating layer 2, and a substrate potential is supplied to the channel region, thereby preventing the channel region from floating.

On the other hand, the p-channel MISFET Qp is formed on the main surface of the active region of the n ⁻ -type semiconductor layer 3a surrounded by the field insulating film 6. The p-channel MISFET Qp is composed of p-type semiconductor regions (source region, drain region) formed in the semiconductor layer 3a, a gate insulating film 8 formed on the surface of the semiconductor layer 3a, and a gate electrode 9 formed on the gate insulating film 8. The semiconductor layer 3a directly below the gate electrode 9, i.e., the channel region, is electrically connected to the n-type well 4 through the opening 5 in the insulating layer 2.

To another region of the n ⁻ type semiconductor layer 3 a, a wiring 12 is connected through a connection hole 11 formed in an insulating film 10, and a well potential of about 2 V is supplied. This semiconductor layer 3 a is electrically connected to an n type well 4 through an opening 5 in the insulating layer 2 below it, similar to the semiconductor layer 3 a in which the p channel type MISFET Qp is formed.

In this way, the p-channel MISFET Qp electrically connects the channel region to the n-type well 4 through the opening 5 in the insulating layer 2, and supplies a well potential to this channel region, thereby preventing the channel region from floating.

According to this embodiment configured as described above, the threshold voltage can be controlled without thinning the semiconductor layers 3 a, 3 b until the channel region is completely depleted when a gate voltage is applied. This prevents an increase in the resistance of the source and drain regions (n-type semiconductor region 7, p-type semiconductor region 13) and improves the current drive capabilities of the n-channel MISFET Qn and the p-channel MISFET Qp. Furthermore, a decrease in the threshold voltage due to the manifestation of the parasitic bipolar transistor effect can be prevented, and the threshold voltage can be set to an enhancement type.

Furthermore, according to this embodiment, a fixed potential is supplied to the channel region through the opening 5 in the insulating layer 2 below the semiconductor layers 3a and 3b, thereby preventing a reduction in the effective gate width and improving the current driving capability of each of the n-channel MISFET Qn and the p-channel MISFET Qp. Furthermore, an increase in the junction capacitance of the source and drain regions (n-type semiconductor region 7 and p-type semiconductor region 13) can be prevented, thereby improving the operating speed.

Furthermore, according to this embodiment, heat generated during operation of the n-channel MISFET Qn and the p-channel MISFET Qp can be dissipated to the semiconductor substrate 1 through the openings 5 in the insulating layer 2 below the semiconductor layers 3a and 3b, thereby improving the heat dissipation properties of the SOI substrate.

Next, a method for manufacturing the CMOS gate array of this embodiment will be described with reference to FIGS.

First, as shown in FIG. 3, a p-type semiconductor substrate 1 is heat-treated to form an insulating layer 2 of silicon oxide on its surface. Then, as shown in FIG. 4, using the insulating layer 2 and photoresist 15 as a mask, n-type impurities (phosphorus or arsenic) are implanted into the semiconductor substrate 1 in the region where the p-channel MISFET Qp is to be formed, thereby forming an n-type well 4.

Next, after removing the photoresist 15, the insulating layer 2 is dry-etched using a new photoresist 16 as a mask, as shown in FIG. 5, to form an opening 5 reaching the semiconductor substrate 1 and an opening 5 reaching the n-type well 4.

As shown in FIG. 6 , the openings 5 are formed at equal intervals along directions perpendicular to each other on the main surface of the insulating layer 2. The openings 5 are formed so that their diameters are smaller than the gate length of the MISFET gate electrodes. In this embodiment, at least one opening 5 is disposed below the channel region of the MISFET, and therefore the interval between adjacent openings 5 is set to 1/n (n is a natural number) of the interval between adjacent MISFET gate electrodes along the gate length direction.

7, p ⁻ semiconductor layer 3 b is selectively epitaxially grown on the surfaces of semiconductor substrate 1 and n-type well 4 exposed at the bottom of opening 5. The semiconductor layer 3 b is grown until the semiconductor layers 3 b grown through each opening 5 are connected to each other on top of insulating layer 2 and cover the entire surface of insulating layer 2.

Next, as shown in Figure 8, the semiconductor layer 3b is thinned by CMP (Chemical Mechanical Polishing) or etch-back, and its surface is planarized. This semiconductor layer 3b has a thickness that is at least large enough to prevent complete depletion of the channel region when a gate voltage is applied.

Next, as shown in FIG. 9, using the photoresist 17 as a mask, n-type impurities (phosphorus or arsenic) are implanted into the semiconductor layer 3b in the region where the p-channel MISFET Qp is formed, thereby forming an n-type semiconductor layer 3a on the n ^- type well 4.

Next, after removing the photoresist 17, as shown in FIG. 10, a thick field insulating film 6 for element isolation and a gate insulating film 8 are formed on the surfaces of the semiconductor layers 3a and 3b, respectively. Then, as shown in FIG. 11, the polycrystalline silicon film deposited by the CVD method is patterned to form gate electrodes 9 on the gate insulating films 8 of the semiconductor layers 3a and 3b.

Next, as shown in FIG. 12, p-type impurities (boron) are implanted into the semiconductor layer 3a to form the source and drain regions (p-type semiconductor regions 13) of the p-channel MISFET Qp, and n-type impurities (phosphorus or arsenic) are implanted into the semiconductor layer 3b to form the source and drain regions (n-type semiconductor regions 7) of the n-channel MISFET Qn.

Thereafter, a silicon oxide insulating film 10 is deposited by CVD on the top of each of the n-channel MISFET Qn and the p-channel MISFET Qp. Wiring 12 is then connected to the source and drain regions (p-type semiconductor regions 13) of the p-channel MISFET Qp and the source and drain regions (n-type semiconductor regions 7) of the n-channel MISFET Qn through connection holes 11 formed in the insulating film 10. Wiring 12 for supplying a well potential is also connected to the semiconductor layer 3a in another region, and wiring 12 for supplying a substrate potential is also connected to the semiconductor layer 3b in another region, thereby completing the CMOS circuit shown in FIGS. 1 and 2 .

(Second Embodiment) In the first embodiment, we described the use of an SOI substrate composed of a semiconductor substrate 1, an insulating layer 2, and semiconductor layers 3a and 3b made of epitaxial single-crystal silicon. However, we can also use an SOI substrate obtained by the SIMOX (Separation by Implanted Oxygen) method, in which oxygen ions are implanted into the semiconductor substrate 1 made of single-crystal silicon, and then the semiconductor substrate 1 is heat-treated to form an insulating layer of silicon oxide within it.

In this case, first, as shown in FIG. 13, an insulating film (or photoresist) 18 such as silicon oxide formed on a p-type semiconductor substrate 1 is used as a mask to implant n-type impurities (phosphorus or arsenic) into the semiconductor substrate 1 in the region where the p-channel MISFET Qp is to be formed, thereby forming an n-type well 4, and then the insulating film 18 is removed, and subsequently, as shown in FIG. 14, a p ⁻ -type semiconductor layer 19 b is epitaxially grown on the entire surface of the semiconductor substrate 1.

Next, as shown in FIG. 15 , island-shaped insulating film patterns 20 are formed at equal intervals on semiconductor layer 19 b, and then oxygen ions are implanted into semiconductor layer 19 b using these insulating film patterns 20 as a mask. The island-shaped insulating film patterns 20 are formed, for example, by patterning a silicon oxide film formed on semiconductor layer 19 b. The dimensions and spacing of these insulating film patterns 20 are set to be the same as those of the openings 5 formed in insulating layer 2 of the SOI substrate used in the first embodiment.

Next, after removing the insulating film pattern 20, the semiconductor substrate 1 is heat-treated to react silicon with oxygen, thereby forming an insulating layer 21 made of silicon oxide at the bottom of the semiconductor layer 19b, as shown in FIG. 16. At this time, no insulating layer 21 is formed in the region below the insulating film pattern 20 where oxygen ions were not implanted, resulting in an SOI substrate having a structure substantially similar to that shown in FIG. 8 of the first embodiment.

Thereafter, a CMOS gate array can be formed according to the steps shown in FIGS. 9 to 12 of the first embodiment.

The invention made by the inventor has been specifically described above based on the examples. However, the present invention is not limited to the first and second examples described above, and various modifications are possible without departing from the spirit and scope of the invention.

In the first and second embodiments, a fixed potential is supplied to each channel region of the n-channel MISFET Qn and the p-channel MISFET Qp that constitute the CMOS gate array. However, for example, a fixed potential may be supplied only to the channel region of the n-channel MISFET Qn.

Furthermore, in the first embodiment, when the insulating layer 2 formed on the semiconductor substrate 1 is etched to form the opening 5, the insulating layer 2 may be entirely removed from a portion of the semiconductor substrate 1, as shown in FIG. 17 . In this case, the region from which the insulating layer 2 is removed does not have an SOI structure, and therefore a MISFET with characteristics different from those of the MISFET formed on the SOI substrate can be formed on the semiconductor layer 3 b epitaxially grown on the semiconductor substrate 1 in this region. In other words, MISFETs with different characteristics can be mixed on the same semiconductor substrate 1.

The present invention can be applied not only to CMOS gate arrays but also to circuits constructed solely with n-channel MISFETs. In other words, the present invention can be widely applied to semiconductor integrated circuit devices composed of MISFETs formed on an SOI substrate.

INDUSTRIAL APPLICABILITY As described above, the semiconductor integrated circuit device of the present invention can suppress fluctuations in the threshold voltage of MISFETs formed in the semiconductor layer of an SOI substrate, ensuring stable operation of the MISFETs. Therefore, it is suitable for use in various LSIs that use SOI substrates.

───────────────────────────────────────────────────── (Note) This publication is based on the publication published internationally by the International Bureau of Patents (WIPO). The effect of the international publication of the Japanese patent application (Japanese utility model registration application) related to this publication arises pursuant to Article 184-10, Paragraph 1 of the Patent Act (Article 48-13, Paragraph 2 of the Utility Model Act) and is unrelated to this publication.

Claims (10)

[Claims] 1. A semiconductor integrated circuit device in which a MISFET is formed on the main surface of a semiconductor layer formed on a semiconductor substrate with an insulating layer interposed therebetween, wherein an opening is provided in the insulating layer below a channel region of the MISFET, and the channel region and the semiconductor substrate are electrically connected through the opening. 2. A semiconductor integrated circuit device according to claim 1, wherein the openings are provided in the insulating layer at equal intervals. 3. A semiconductor integrated circuit device according to claim 1, wherein a fixed potential is supplied to the semiconductor substrate through the semiconductor layer in a region where the MISFET is not formed and the opening provided in the insulating layer thereunder. 4. The semiconductor integrated circuit device according to claim 1, wherein the spacing between adjacent openings is set to 1/n (n is a natural number) of the spacing between gate electrodes of adjacent MISFETs along the gate length direction. 5. A semiconductor integrated circuit device according to claim 1, wherein an n-channel MISFET is formed in the first region of the semiconductor layer, and a p-channel MISFET is formed in the second region of the semiconductor layer. 6. A semiconductor integrated circuit device according to claim 5, wherein the source and drain regions of the n-channel MISFET and the p-channel MISFET have their bottoms in contact with the insulating layer. 7. A method for manufacturing a semiconductor integrated circuit device, in which a MISFET is formed on a main surface of a semiconductor layer formed on a semiconductor substrate with an insulating layer interposed therebetween, comprising: (a) forming an insulating layer on the semiconductor substrate, and then etching the insulating layer to form a plurality of openings at predetermined intervals that reach the semiconductor substrate; (b) epitaxially growing a semiconductor layer on the semiconductor substrate exposed at the bottom of each opening, thereby covering the entire upper surface of the insulating layer with the semiconductor layer; (c) thinning the semiconductor layer to a predetermined thickness, and then forming an insulating film for element isolation on the main surface of the semiconductor layer; (d) forming a MISFET on the main surface of the semiconductor layer, a portion of whose channel region is located above the opening. 8. A method for manufacturing a semiconductor integrated circuit device, in which a MISFET is formed on a main surface of a silicon substrate having an insulating layer formed therein, comprising: (a) forming island-shaped patterns spaced apart at predetermined intervals on the silicon substrate, and then implanting oxygen ions into the silicon substrate using the island-shaped patterns as a mask; (b) heat-treating the silicon substrate to react silicon with oxygen, thereby forming a silicon oxide layer inside the silicon substrate except for areas under the island-shaped patterns; and (c) forming an insulating film for element isolation on the main surface of the silicon substrate, and then forming a MISFET on the main surface of the silicon substrate, with a portion of the channel region located in an area where the silicon oxide layer is not formed. 9. A semiconductor wafer having an SOI structure in which a semiconductor layer is formed on a semiconductor substrate via an insulating layer, wherein openings are formed in the insulating layer at predetermined intervals, and the semiconductor layer is formed on top of the insulating layer, including the interior of each opening. 10. The semiconductor wafer according to claim 9, wherein the insulating layer is not formed in a partial region of the semiconductor substrate.