JPWO1993023825A1 - Cartridges for electronic devices - Google Patents

Abstract

(57) [Abstract] This publication contains application data prior to electronic filing, so abstract data is not recorded.

Description

Detailed Description of the Invention

Cartridges for electronic devices

[Technical Field]

The present invention relates to a cartridge for an electronic device that is inserted into an electronic device such as a printer.

[Background Art] In recent years, electronic devices based on digital operations, such as personal computers, word processors, and workstations, as well as printers, facsimiles, electronic organizers, electronic musical instruments, electronic cookers, and electronic cameras incorporating microprocessors, have come to be used in a wide range of areas of society. Microprocessors are also widely used in automobiles, robots, machine tools, and various electrical appliances. These devices based on digital logic operations offer the advantage of more flexible control than simple feedback control achieved solely by hardware, as well as the ability to change their actual functions by modifying the software. Therefore, even with the same hardware, it is possible to achieve completely different control simply by changing the contents of the ROM that stores the processing procedures. Another advantage is that functionality can be upgraded simply by modifying the software. However, in reality, this is not always the case. The processor's capabilities are determined by its hardware, such as the number of operations per unit time, the number of bits it can handle at one time, and the width of the bus over which data is transferred. Therefore, software upgrades offer only limited improvements, such as improved ease of use, and do not actually significantly improve the capabilities of existing electronic equipment. Furthermore, software upgrades are often difficult because software is often burned into ROM, requiring ROM replacement. This makes software upgrades difficult except for models designed with ROM replacement in mind and those in which the software is provided on exchangeable media such as flexible disks. While there are so-called accelerators for personal computers, which involve replacing the microprocessor and other components to improve the overall computer's functionality, these require replacing the CPU on the motherboard, making them difficult for anyone to perform. When it comes to consumer electronic devices with built-in microprocessors, such as printers, fax machines, electronic organizers, electronic musical instruments, electronic cookers, and electronic cameras, as well as industrial electronic devices such as automotive 3I components, robots, and machine tools, and even various electrical appliances, such functional upgrades and modifications are typically not given the same consideration. This problem has been addressed by the development of page printers and other electronic devices. Let me explain this in more detail using an example. In recent years, page printers such as laser printers have become extremely popular, and are fast becoming the mainstream device for high-speed output of data from combiators. Laser printers have been developed with a resolution of 240 to 800 DPI and a printing capacity of several pages per minute. These printers use a xerography unit with a photosensitive drum as the printing engine, and the processes of charging, exposure, toner application, and transfer are performed continuously in synchronization with the rotation of the photosensitive drum. Therefore, the image for one page is stored in memory before the print process is initiated. Therefore, the image development memory provided in a page printer must have the capacity to store at least one page's worth of image, and if the image data is not compressed, this capacity is determined by the resolution and the size of the paper that can be processed. For example, Considering a printer with a resolution of 300 DP and paper dimensions of 8 inches wide and 10 inches high, a printer would need to handle a total of 8x10x300x300 = 7,200,000 pixels, requiring at least 0.9 megabytes of memory. Furthermore, if the print data received from an external computer is the bit image of the image to be printed, the printer simply receives the data and stores it sequentially in memory, and processing speed depends primarily on the data transfer rate. Parallel transfer, such as that based on the Centronics standard, is quite fast, so it is highly unlikely that the transfer rate will fall below the printing capability of the xerography unit. However, printers that receive print data containing information such as character codes and line and column pitch and render it as an image, or printers that receive and interpret programs written in a page description language, require processing to calculate and generate a bit image based on the print data. However, this method significantly reduces overall processing speed compared to simple bit image transfer. In other words, the printer's processing speed is primarily determined by the processor's capabilities and memory access time, resulting in a speed significantly lower than the printing capability of the xerography unit itself. For example, consider a page printer capable of printing 10 pages per minute. The time allowed to prepare image data for one page is only six seconds. If all 0.9 megabytes of data are to be extracted in this time, the processing time allowed per byte is only 6.67 microseconds (6 seconds 70.9 megabytes). This processing speed is only achievable with the high-speed RISC-type processors currently available on the market. In contrast, xerography units often already have a printing capability of around 10 pages per minute. Therefore, currently, the processing capability of the control unit that processes the print data is the key to improving overall printing speed. This is a bottleneck in the development of page printers. Some page printers have expandable internal memory capacity, while others have pre-installed expansion slots where cartridges containing fonts and programs can be inserted to enhance functionality. However, while memory expansion can improve processing speed, it does not improve processing power itself. For example, to expand the processing capabilities of laser printers that only support a specific page description language, other page description language interpreter programs are supplied on IC cards or other cartridges. These cartridges contain the programs in mask ROM and are inserted into the printer's expansion slot. This section explains the cartridges that provide the page language interpreter programs. The printer's control unit reads a specific address assigned to the cartridge immediately after power-on, for example. When a cartridge containing a page language program is inserted, a specific code is returned. The control unit then learns that the cartridge is a page language program. This transfers control of the printer to the interpreter program located inside the cartridge. While this allows the printer to interpret data received from an external source in accordance with the page language, it does not improve processing speed. In fact, adopting a high-level page description language often results in a slower overall printing speed. To address this issue, a cartridge with a microprocessor separate from the printer itself was invented. This cartridge receives print data from the printer, and the microprocessor within the cartridge generates image data based on the received print data. The cartridge's housing is made of aluminum, which dissipates heat generated by the internal microprocessor. However, this metal housing acts as an antenna, increasing unwanted electromagnetic radiation. However, this can cause noise in the cartridge itself or in surrounding electronic devices, resulting in malfunctions. The cartridge also has a problem with heat dissipation that must be solved. The microprocessor used in the cartridge is an electronic circuit containing tens of thousands to hundreds of thousands of elements, which perform switching operations in response to a clock signal with a frequency of 20-40 MHz or higher. Consequently, the microprocessor generates a considerable amount of heat during operation. Therefore, if the heat generated by the microprocessor is not dissipated to the outside, the microprocessor temperature will rise, causing the microprocessor to malfunction or even destroy its internal elements. To prevent malfunctions and damage to the elements, the maximum allowable humidity for the microprocessor case is set at approximately 80°C. To maintain the surface temperature of the case below the allowable value, it is important to devise a cartridge structure that allows heat to be easily dissipated from the microprocessor to the outside. However, in the past, cartridges installed in printers did not allow the microprocessor to dissipate heat to the outside. Since there were no cartridges equipped with such a heat dissipation mechanism, the heat dissipation structure of the cartridge was also unknown. This invention was made to solve the above-mentioned problems in the prior art, and its primary object is to provide an electronic device cartridge containing a circuit element, such as a microprocessor, that executes predetermined processing based on print data received from a printer body, and that reduces unnecessary electromagnetic radiation to the outside. An additional object of this invention is to provide an electronic device cartridge that can efficiently cool the internal circuit element. [DISCLOSURE OF THE INVENTION] To solve the above-mentioned problems, the electronic device cartridge of this invention is an electronic device cartridge that is inserted through a specified insertion port into an electronic device equipped with a first processor capable of logical operations, and includes a conductive shielding member and connecting means for electrically connecting the shielding member to the conductive members of the electronic device. By including the conductive shielding member, this cartridge reduces the amount of electromagnetic noise emitted to the outside. The cartridge further includes a second processor and a circuit board on which the second processor is mounted, and the connecting means may include means for electrically connecting the shielding member, the power supply wiring of the circuit board, and the conductive members of the electronic device. The connecting means electrically connects the shielding member, the power supply wiring, and the conductive members of the electronic device, thereby stabilizing the potential of the shielding member and thereby preventing the generation of electromagnetic noise. The cartridge may also include a housing for housing the circuit board, the housing including the shielding member. At least a portion of the housing may be made of metal, and at least a portion of the housing may have a conductive layer. The housing includes first and second housing elements that fit together to house the board, and preferably, a conductive layer is formed on the mating surfaces of the first and second housing elements at least in the protruding portions of the cartridge that protrude from the electronic device when the cartridge is inserted into the electronic device. In the cartridge, the housing is formed by first and second housing elements that fit together, and a conductive layer is formed on each of the mating surfaces of the first and second housing elements, thereby preventing electromagnetic noise from radiating from the joint between the two housing elements. In one embodiment of the present invention, one of the first and second housing elements is made of plastic, and the other is made of metal. The connecting means preferably electrically connects the power supply wiring of the board to the shielding member at multiple locations. This configuration reduces the impedance between the power supply wiring of the board and the shielding member, thereby effectively preventing the generation of shoulder frequency noise. If the housing has a through hole, the connecting means preferably further includes means for electrically connecting the power supply wiring of the board to the shielding member at at least one location between both ends of the through hole. This configuration shortens the wavelength of the electromagnetic waves emitted to the outside from the through hole, thereby reducing harmful electromagnetic noise. This is effective in reducing the risk of electrical shock. The connection means may include a conductive elastic member fixed to the shielding member, the conductive elastic member having a protruding portion protruding outward from a port provided in the housing and configured to electrically contact a conductive member of the electronic device when the cartridge is inserted into the electronic device. Alternatively, the connection means may include a plurality of the conductive elastic members, at least one of which electrically contacts a conductive member of the electronic device when the cartridge is inserted into the electronic device. Furthermore, the plurality of conductive elastic members may electrically connect the shielding member to the power supply wiring of the board. In terms of heat dissipation characteristics, the connection means preferably includes a metal heat dissipation member fixed to the metal housing element and positioned inside the housing facing the top surface of the second processor, and an interposition member interposed between the heat dissipation member and the top surface of the second processor and in close contact with the heat dissipation member and the second processor. This allows heat generated by the second processor to be dissipated to the outside via the heat dissipation member and the metal housing element. Furthermore, by providing an elastic member for pressing the second processor toward the heat dissipation member, thermal resistance between the second processor, the interposing member, and the heat dissipation member can be reduced. Incidentally, if the board includes an expansion memory connector, memory can be easily added as needed depending on the cartridge's intended use. In this case, the housing is preferably provided with an expansion slot for inserting the expansion memory into the expansion memory connector and a removable expansion slot cover, and the expansion slot cover is preferably located in a position that is hidden within the electronic device when the cartridge is inserted into the electronic device. This prevents the expansion memory from being accidentally inserted or removed while the cartridge is in use. Incidentally, if the expansion memory is configured as an IC card, memory expansion is easy. Incidentally, if the electronic device cartridge includes a connecting means for mechanically connecting the electronic device main body and the electronic device cartridge, theft of the electronic device cartridge can be prevented. The connecting means may also include a locking means and a switch means for powering on the electronic device cartridge in response to the locking of the locking means.An electronic device cartridge according to another configuration of the present invention is a cartridge for insertion into an electronic device through a predetermined insertion port, and includes a circuit board having a digital processor mounted thereon, a shielding member made of a conductive material, a housing for accommodating the circuit board, and grounding means for electrically connecting the conductive portion of the electronic device, the power supply wiring of the circuit board, and the shielding member. Furthermore, a cartridge for an electronic device according to still another aspect of the present invention is a cartridge for an electronic device that is inserted through a predetermined insertion opening into an electronic device having a first processor capable of logical operations and a connector to which at least an address signal line of the first processor is connected, and that includes a second processor, data extraction means for extracting data reflected in an address signal output from the electronic device, a housing having a conductive shielding member and housing the second processor, and connection means for electrically connecting the conductive member of the electronic device, the power supply wiring of the board, and the shielding member.A cartridge for an electronic device according to another aspect of the present invention is a cartridge for an electronic device that is inserted through a predetermined insertion opening into an electronic device that includes a first processor capable of logical operations, first storage means for storing the processes to be executed by the processor, a connector to which at least an address signal line of the first processor is connected, and address output means for reflecting data to be transferred externally in an address signal and outputting the address signal through the connector. a cartridge for an electronic device inserted through an electronic device cartridge, the cartridge comprising: a second processor; second storage means for storing a processing procedure executed by the second processor; data retrieval means for retrieving data reflected in an address signal output from the electronic device from the address signal; a circuit board mounting the second processor, second storage means, and data retrieval means; a housing for housing the circuit board and including a conductive shielding member; and grounding means for electrically connecting a conductive portion of the electronic device, the power supply wiring of the circuit board, and the shielding member. The present invention also includes an electronic system constituted by a combination of each of the above-mentioned cartridges for an electronic device and an electronic device.

[Brief Description of the Drawings] Fig. 1 is a perspective view showing a cartridge according to one embodiment of the present invention. Fig. 2 is an exploded perspective view of the cartridge according to the embodiment. Fig. 3 is an enlarged perspective view of the printed circuit board. Fig. 4 is a diagram showing the lower case. Fig. 5 is a plan view of the printed circuit board. Fig. 6 is a side view showing the printed circuit board being placed in the lower case. Fig. 7 is an enlarged cross-sectional view of the cartridge's microprocessor. Fig. 8 is a perspective view showing the cartridge inserted into a first type printer body. Fig. 9 is a perspective view showing the cartridge inserted into a second type printer body. Fig. 10 is a diagram showing the cartridge and the printer body when inserted into the first type printer body. Figure 11 is a longitudinal cross-sectional view of the cartridge and printer frame inserted into the second type printer body. Figure 12 is a graph showing the results of electromagnetic noise measurements before and after electromagnetic noise countermeasures. Figure 13 is a conceptual diagram showing a cartridge connected to the printer body by a chain. Figure 14 is a conceptual diagram showing a cartridge with a key locking mechanism. Figure 15 is a block diagram showing the overall configuration of the printer and cartridge. Figure 16 is an explanatory diagram showing the signal line configuration in the connector CNI 1. Figure 17 is an explanatory diagram showing the address map of cartridge 503 as seen from the electronic control unit 1501 side. Figure 18 is a diagram showing the cartridge as seen from the microprocessor 601 side. FIG. 19 is a block diagram showing the internal configuration of cartridge 503. FIG. 23 is a circuit diagram showing an example of the configuration of the interrupt request register 640. FIG. 20 is a circuit diagram showing an example of the configuration of the polling command register 643. FIG. 2 is a diagram showing the contents of the status register 645. FIG. 22 is a circuit diagram showing an example of the configuration of the read/write control circuit 620. FIG. 24 is a flowchart showing the processing on the electronic control unit 501 side that realizes data transfer using the continuous output control circuit 620. FIG. 25 is a diagram showing the data structure in ROM 671. FIG. 26 is a flowchart showing the processing on the cartridge 503 side that realizes data transfer using the continuous output control circuit 620. FIG. 27 is a flowchart showing the processing performed by the electronic control unit 501 to implement data transfer using the FIFO control circuit 623. FIG. 28 is a flowchart showing the processing performed by the cartridge 503 to implement data transfer using the FIFO control circuit 623. FIG. 29 is a circuit diagram showing an example configuration of the double-bank control circuit 624. FIG. 30 is a flowchart showing the processing for initiating data transfer using the double-bank control circuit 624. FIG. 31 is a flowchart showing the response processing performed by the electronic control unit 1501. FIG. 32 is a flowchart showing the processing performed by the electronic control unit 1501 to implement data transfer using the double-bank control circuit 624. FIG. 33 is a flowchart showing the processing performed by the cartridge 503 to implement data transfer using the double-bank control circuit 624. FIG. 34 is a timing chart showing the timing of printing image data by controlling the laser engine 505.

[Explanation of symbols]

1, 1a, 1b Printer body 15 Xerography unit 34 Data bus 36 Bus driver 50 Cartridge 5B ROM 68 Data selector 100 Upper case 102 Heat dissipation layer silicone rubber 104 Grounding spring member 106 Expansion memory slot 108 End face 110 Metal plate 120 Lower case 122 Spring member ! 24 Engagement portion 126 Pressing silicone rubber 128 Rubber retaining portion 132 Opening 140 Lower cap 142 Through hole 150 Upper cap 160 Screw 180 Metal frame 】82 Metal frame 200 RC card 500 Bridge? r 501 Electronic Control Unit 503 Cartridge 505 Laser Engine 507 Work Stage Unit 510 CPU 11 ROM 512 RAM 514 Data Input Port 515 Line Buffer 518 Pass Line 517 Register 518 Console Panel 519 Console Panel I/F 520 Double Buffer Circuit 550 Printed Circuit Board 551 Plug Unit 601 Microprocessor 602 Memory Unit 603 ASIC 603 Data Transfer Control Section 80B ROM 808 ROM 610 Selector 810 Data Selector 11 RAM 615 Expansion RAM Interface 617 Tri-State Buffer 818 ROM 619 Tri-State Buffer 1 620 Read Control Circuit 821 FIFO Memory 623 FIFO Control Circuit 624 Double Bank Control Circuit 635 Bus Control Unit 637 Reset Element 640 Interrupt Request Register 643 Command Register 645 Status Register 647 Transfer Flag Register 649 FROM Control Register 650 Control Register 851 Latch 853 FIFO Register 654 FIFO Write Circuit 655 FIFO Read Register 657 Latch 658 Buffer 661 Oscillator 665 Oscillator 670 EEFROM 671 ROM 674 D-type Flip-Flop 880 NAND Gate 681 Data Selector 682 Data Selector 684-686 Tristate Buffer 691 RAM 694, 695 OR Gate 696 Inverter 520A RAM 520B RAM 520C Memory Write Controller 520D Memory Read Controller 601p Pin 640a Flip-Flop 640a Interrupt Request Register 643a Off-Chip D-Type Flip-Flop 643c D-Type Flip-Flop 6521 Latch 7900 User Pull Gate AAB Address Bus CAB Address Bus CDB Data Bus CN10 Connector CNII Connector

BEST MODE FOR CARRYING OUT THE INVENTION

The embodiments are described in the following sections. [i] Cartridge Structure A. Cartridge Structure B. Electromagnetic Noise Test Results C. Modified Cartridge Structure [ii] Electrical Configuration of the Printer and Cartridge A. Overall Configuration of the Printer and Cartridge B. Cartridge Address Space C. Internal Configuration of the Cartridge D. Description of the Data Transfer Control Unit 603 E. Description of Each Register F. Configuration and Function of the Output/Open Control Unit 620 G. Configuration and Function of the FIFO 11111 Loopback 623 H. Configuration and Function of the Double Bank Control Circuit 624 I. Printing Image Data [iii] Other [i] Cartridge Structure A. Cartridge Structure Figure 1 is a perspective view showing the structure of a printer cartridge as an embodiment of this invention, and Figure 2 is an exploded perspective view. This cartridge 503 is designed to be inserted into the font cartridge insertion slot of the printer. However, as described below, this cartridge also has the function of receiving print data from the printer and converting the received print data into image data. This cartridge 503 has a structure in which a multilayer printed circuit board 550 (hereinafter simply referred to as the "printed circuit board") is interposed between an upper case 100 with a concave interior and a plate-like lower case 120. A lower cap 140 and an upper cap 150 are attached to the connector side of the cartridge 503. The upper case 100, upper cap 140, and lower cap 150 are made of ABS resin, while the lower case 120 is made of aluminum. A conductive layer is formed on the inner surface of the upper case 100, which, together with the lower case 120, forms a frame ground. The conductive layer on the inner surface of the upper case 100 is formed by electroless copper-nickel plating. However, this conductive layer may also be formed using other well-known methods, such as painting with conductive paint or vacuum deposition of aluminum. The upper case 100 may also be manufactured by molding conductive plastic. In the following, cap 140 will be referred to as the "cap 140." The side with the microprocessor 601 is called the front of the cartridge, and the side with the microprocessor 601 is called the rear of the cartridge. A plug portion 551 is formed at the front of the printed circuit board 550, and circuit elements such as the microprocessor 801 are attached at the rear. Four grounding spring members 104 are fixed to the periphery of the printed circuit board 550, two of which are located in the center of the cartridge insertion direction and the other two at the rear of the cartridge. The spring members 104 serve to electrically connect the ground wiring of the printed circuit board 550 to the conductive layer on the inner surface of the upper case 100. Two grounding spring members 122 are fixed to the front of the lower case 120 to ensure a ground connection with the printer body. The grounding spring member 122 has the shape of a bird with its wings spread, with first bent portions 122a, corresponding to the left and right wings, bending upward, and second bent portions, corresponding to the bird's legs, bending downward in a semicircular arc. The first bent portion 122a electrically connects the lower case 120 to the ground wiring of the printed circuit board 550. The second bent portion protrudes from the cartridge 503 through an opening 132 provided in the lower case 120 and electrically connects the grounding portion of the printer body to the lower case 120. A wall-shaped mating portion 124 protruding from the flat plate portion 121 is provided on the periphery of the lower case 120. The mating portion 124 mating with the side of the upper case 100 forms the main structure of the approximately rectangular parallelepiped housing. At the rear of the lower case 120, a cylindrical pressing silicone rubber 12B is fitted into a rubber holder 128 on the inner surface of the lower case to press the printed circuit board 550 upward. The pressing silicone rubber 126 serves to press the printed circuit board 550, located directly below the microprocessor 601, upward. A sheet-like heat-dissipating silicone rubber 102 is interposed between the top surface of the microprocessor 601 and the inner surface of the upper case 100 to improve adhesion and thermal conductivity. In addition, an aluminum heat sink 110 is fixed to the lower case 120 with screws so as to cover the top of the microprocessor 601. When the pressing silicone rubber 126 presses the printed circuit board 550 upward, the microprocessor 601 is also pressed upward, improving adhesion between the microprocessor 601 and the heat-dissipating silicone rubber 102, and between the heat-dissipating silicone rubber 102 and the heat sink 110. As a result, heat generated by the microprocessor 601 is conducted to the lower case 120 via the heat sink 110 and then dissipated from the lower case 120 to the outside. During assembly, first, two grounding spring members 122 are fixed to the lower case 120, and then the pressing silicone rubber 126 is fitted into the rubber holder 128. Meanwhile, various circuit elements are attached to the printed circuit board 550, and four grounding spring members 104 are inserted into the designated holes in the printed circuit board 550 and secured with solder. Next, the printed circuit board 550 is placed on the lower case 120, and a screw is used to secure one of its rear corners (on the microprocessor 601 side). The heat sink 110 is then secured to the side of the fitting 124 of the lower case 120 with a screw. The upper case 100 is then fitted to the lower case 120, and the lower cap 140 is inserted. At this time, the two screw through-holes 141 on the lower cap 140 are inserted under the corresponding portions of the upper case 100, and the plugs 551 pass through the through-holes 142 on the lower cap 140. The upper case 100 is secured with screws at 31° on the front side. Finally, the upper cap 150 is fitted into the upper case 100, completing the cartridge 503 shown in Figure 1. Incidentally, a button lock 154 with a spring 152 housed inside is provided on each side of the upper cap 150. The button locks 154 are biased outward by the springs 152. When the two button locks 154 are pressed inward, their tabs disengage from the engaging portions of the upper case 100, and when the button locks 154 are released, they engage with the retaining portions. Figure 2 also shows an IC card 200. The IC card 200 is an expansion memory containing multiple dynamic RAMs and can be inserted into the cartridge 503 as needed. To insert the IC card 200, first remove the top cap 150 and insert the IC card 200 into the expansion memory slot 106 provided in the upper case 100. The IC card 200 then plugs into the IC card connector 210 in the printed circuit board 550. Then, when the top cap 150 is attached, the IC card returns to its original shape as shown in Figure 1. In this embodiment, the removable top cap 150 can be removed to insert the IC card 200, facilitating memory expansion. Furthermore, by providing the top cap 150 at the front of the cartridge 503, the IC card 200 cannot be inserted while the cartridge 503 is inserted in the laser printer body. Figure 3 is an enlarged perspective view of the printed circuit board 550. As shown in Figure 3, a microprocessor 601 is attached to the rear end of the top surface of the printed circuit board 550, and an attachment plug 551 is formed at the other end for connecting to a connector on the printer body. Surrounding the microprocessor 601 are four ROMs 806-609 that store control programs for the microprocessor 601, four address buffers 617, and clock oscillators 661 and 865. Additionally, an IC card connector 210 is provided slightly forward from the center of the printed circuit board 550. Mounted on the back side of the printed circuit board 550 are various circuit elements, such as an ASIC (application-specific integrated circuit) containing control circuits and registers, and a ROM (hereinafter referred to as the "printer ROM") storing the processing program for the processor within the printed circuit board. For ease of illustration, the wiring patterns formed on the front side of the printed circuit board 550 are omitted. Microprocessor 601 is a pin grid array (PGA) type element, while the others are single-ended, single-ended package (SOP), or quadrature flat package (QFP) type elements. Microprocessor 801, for example, is a R The ISC processor used is the AMD Am29030 (clock frequency 25 MHz). As mentioned above, this cartridge 503 is inserted into the font cartridge slot of the printer body. While a typical font cartridge simply contains a ROM that stores font data, the cartridge 503 of this embodiment is equipped with a microprocessor 601 and ROMs 806-609 that store the processing program for the microprocessor 601. It also includes a printer-specific ROM and a control circuit including an ASIC. This cartridge 503 is unique in that it is inserted into a connector on the printer body, which is designed to connect to a font cartridge. Therefore, it has a dedicated read line for reading data from the cartridge to the printer body, but no signal line for transferring data from the printer body to the cartridge. In contrast, the cartridge 503 in this embodiment has the function of receiving print data from the printer body and converting this print data into image data using the microprocessor 601. To do this, the print data must be transferred from the printer body to the cartridge using the dedicated read line of the connector. For this purpose, the microprocessor in the printer body executes special processing, as described below. When cartridge 503 is inserted into the printer body, the processor in the printer body reads the identification data stored in the printer body ROM in cartridge 503 upon printer startup. Based on this identification data, the processor in the printer body executes processing according to the processing program stored in the printer body ROM. The processor in the printer body then reads the printer body ROM. The cartridge 503 executes special processing according to the processing program stored in the printer. This special processing involves generating an address that essentially contains one byte of print data (page description language program) and transmitting this address over the address bus from the printer to the cartridge 503. The cartridge ASIC receives this address and decodes it to extract the one byte of print data contained in the address, which it then stores in a designated RAM (described below) within the cartridge. The microprocessor 601 then reads the data stored in this RAM and executes the special processing. The cartridge 503 converts the print data into image data. The converted image data is transferred from the cartridge 503 to the printer, where the xerography unit prints the image. It is preferable to use a processor faster than the printer itself as the microprocessor 601. In this way, the image conversion process that should be performed by the printer itself is performed by the high-speed microprocessor 601, thereby substantially improving the printer's processing speed. The circuitry within the cartridge 503 and its operation will be described in more detail below. Figure FIG. 4(A) is a plan view of the lower case 120, and FIG. 4(B) is a cross-sectional view taken along the line B-B. Note that FIG. 4(B) also depicts a cross-section of the upper case 100. As shown in FIG. 4(A), the lower case 120 is primarily composed of a flat plate portion 121 and a mating portion 124. The mating portion 124 forms a continuous wall around the periphery of the lower case 120, except for a break near the screw hole 125 at the front in the insertion direction. As shown in FIG. 4(B), the mating portion 124 fits into the inner surface of the side of the upper case 100, forming a housing with a roughly rectangular cross-section. As mentioned above, the lower case 120 The upper case 100 is made of aluminum, and a conductive layer is formed on the inner surface of the upper case 100. Therefore, the conductive layers on the outer surface of the mating portion 124 and the inner surface of the upper case 100 overlap each other around the outer periphery of the mating portion 124, which is effective in blocking electromagnetic noise generated by the internal circuit elements. Figure 5 is a bottom view of the printed circuit board 550 (i.e., the side opposite the side on which the microprocessor 601 is mounted). However, Figure 5 shows the state without any circuit elements mounted on it. Multiple GND lands 560, 526, and 570 are located around the periphery of the printed circuit board 550. 564, 566 are formed on the printed circuit board 550. These GND lands are conductive layer regions provided for the signal ground of the printed circuit board 550. As can be seen by comparing with Figure 2, the two GND lands 560 at the rear of the printed circuit board 550 (the upper side in Figure 5) are formed in an area that includes through holes for screws that secure the printed circuit board 550 to the lower case 120 and three small holes for inserting the grounding spring member 104. The two GND lands 562 located approximately in the center of the printed circuit board 550 in the insertion direction are formed in an area that includes three small holes for inserting the grounding spring member 104. In addition, the two GND lands 564 at the front end of the printed circuit board 550 in the insertion direction and the GND land 566 in its center are each formed in an area that includes through holes for screws that secure the printed circuit board 550 to the lower case 120. When the cartridge 503 is assembled, the GND land 560 at the rear of the printed circuit board 550 and the GND land 562 at the center are electrically connected to the conductive layer on the inner surface of the upper case 100 via the grounding spring member 104 (Figure 2). At the same time, the GND land 560 at the rear of the printed circuit board 550 and the GND land 564 at the front are electrically connected to the conductive layer on the inner surface of the upper case 100 via the grounding spring member 104 (Figure 2). 586 contacts the screw holes in the lower case 120, electrically connecting it to the lower case 120. As a result, the grounding wire (hereinafter referred to as "signal ground" or rSG) of the printed circuit board 550 is connected to the conductive layer of the chassis (hereinafter referred to as "frame ground" or rFGJ) at multiple points. By grounding the SG and FC at multiple points in this way, the impedance between the 5G and FC can be reduced, preventing the generation of high-frequency currents. This effectively prevents the generation of electromagnetic noise caused by high-frequency currents. As can be seen in Figure 2, there is no conductive layer in the area of the through-hole 142 of the lower cap 140, making it easy for electromagnetic noise to leak to the outside. As is well known, electromagnetic noise standards (such as Japan's VCCI and the U.S. FCC) regulate a specific frequency range (30 to 1,000 ohms), and reducing electromagnetic noise in this range can prevent harmful electromagnetic noise. Ground land 566 (IP15) located near the center of plug portion 551 is designed to reduce harmful electromagnetic noise by reducing the wavelength of the electromagnetic noise emitted from through-hole 142 to approximately 172 ohms (i.e., approximately doubling the frequency). Figure 6 shows the electrical connection between printed circuit board 550 and lower case 20 via grounding spring member 122. 6A and 6B are side views illustrating the electrical connection between the printed circuit board 550 and the lower case 120. FIG. 6A shows the state before the printed circuit board 550 is placed on the lower case 120, and FIG. 6B shows the state after placement. As shown in FIG. 6A, there is a gap between the first bent portion 122a of the grounding spring member 122 and the mating portion 124 of the lower case 120. In the state shown in FIG. 6B, the first bent portion 122a is pressed against the printed circuit board 550, but there is a small gap between the mating portion 124 and the bent portion 122a. Because the tip of the bent portion 122a is divided into three, each functions as an almost independent spring member, and the grounding spring member 122 functions as an electrical connection between the first bent portion 122a and the lower case 120. The spring members 122 are electrically connected securely to the ground wiring on the underside of the printed circuit board 550. These grounding spring members 122 are also effective in preventing the generation of electromagnetic noise. The first bent portion 122a may be configured to electrically connect a power supply wiring other than the ground wiring, such as a power supply wiring that supplies a stable voltage (3V, 5V, etc.) to drive the microprocessor 801 and other peripheral circuits, to the lower case 120. It may also be connected to a power supply wiring that provides a stable voltage that is provided separately from such a power supply wiring. Figure 7 shows an enlarged view of the microprocessor 601 portion of the cartridge 503. This is a cross-sectional view of a key part. A pressing silicone rubber 126 is fitted into the rubber retaining portion 128 of the lower case 120, and the pressing silicone rubber 12B presses the printed circuit board 550 upward. The pin 801p of the microprocessor 601 is soldered onto the printed circuit board 550. A heat-dissipating silicone rubber 102 is interposed between the top surface of the microprocessor 601 and the heat sink 110. Heat generated by the microprocessor 601 passes through the heat-dissipating silicone rubber 102, the heat sink 110, and the lower case 120, and is released to the outside from the bottom surface of the lower case 120. The pressing silicone rubber The rubber band 126 presses the printed circuit board 550 upward, improving the adhesion between the microprocessor 601, the heat-dissipating silicone rubber 102, and the heat sink 110, and improving thermal conductivity between them. A material with good thermal conductivity is used for the heat-dissipating silicone rubber 102. For example, Shin-Etsu Polymer Co., Ltd.'s Shin-Etsu Silico Sheet (product name), Shin-Etsu Chemical Co., Ltd.'s TC-CG Type Heat-Dissipating Silicone Rubber Sheet (product name), or Fuji Polymer Industries Co., Ltd.'s Sarcon (product name). All of these have a relatively high thermal conductivity of approximately 1 W/m11 or higher. Furthermore, non-solid materials such as viscous liquids, putty, or grease, such as RTV Rubber Compound (product name) manufactured by Shin-Etsu Chemical Co., Ltd., which solidify upon use, can also be used as the material to be applied to the top surface of the microprocessor 601. By using such non-solid materials, adhesion between the microprocessor 601 and the upper case 100 can be ensured with only a small thickness, making them suitable for heat dissipation even if the material has a relatively low thermal conductivity. The end surface 108 of the upper case 100 shown in Figure 7 has numerous holes formed therein, allowing for easy airflow. These holes are also used to secure the cartridge 503. The end surface 108 is movable to release heat from the inside of the cartridge 503. Furthermore, by drilling numerous holes, the surface area of the end surface 108 is increased, which also improves heat dissipation efficiency. If other heat dissipation measures are sufficient, drilling holes in the end surface 108 is not necessary. Furthermore, in order to reduce electromagnetic noise, it is preferable not to drill holes in the end surface 108. Figures 8 and 9 are perspective views showing the cartridge 503 inserted into the first and second types of printer main bodies 1a and 1b, respectively. Figures 10 and 11 are longitudinal cross-sectional views of the cartridge 503 and the frame of the printer main body 1a+ib in the inserted state. However, the figures For ease of illustration, circuit elements and the like are omitted in Figures 10 and 11. In Figure 10, the plug portion 551 of the printed circuit board is inserted into the printer-side connector CN11. At this time, the spring member 122 on the rear side of the cartridge 503 contacts the metal frame 180 of the printer body 1a. In Figure 11, the spring member 122 on the front side of the cartridge 503 contacts the metal frame 182 of the printer body 1a. In this way, by having one of the two grounding spring members 122 contact a grounded portion of the printer body, the cartridge housing and the printer body are reliably electrically connected. As explained above, the cartridge of this embodiment has the following measures against electromagnetic noise: ■ A conductive layer is formed on the inner surface of the plastic upper case 100, and the lower case 120 is made of aluminum. This forms a conductive layer across the entire inner surface of the cartridge housing, blocking electromagnetic noise. ■ A wall-shaped mating portion 124 is provided on the periphery of the lower case 120, which is designed to fit into the upper case 100. This allows the outer surface of the mating portion 124 to overlap with the conductive layer on the inner surface of the upper case 100, blocking electromagnetic noise. ■ Multiple signal grounds and frame grounds are provided. The signal ground is connected at two points, reducing the impedance between them and suppressing the generation of high-frequency currents. ■ Near the through-hole 142 for the plug portion 551, the signal ground and frame ground are connected at both ends and the center of the plug portion 551, shortening the wavelength (increasing the frequency) of the electromagnetic noise emitted from the through-hole 142. This reduces the harmful wavelength range of electromagnetic noise that is subject to regulation. This cartridge 503 also incorporates the following general electromagnetic noise countermeasures: ■ Decoupling capacitors are installed near the GND pin and power pin of each circuit element. ■ Microprocessor A common-mode choke coil was installed in the power supply wiring of the processor 601. B. Electromagnetic Noise Test Results Figure 12 (A) is a graph showing the electromagnetic noise measurement results for the cartridge before electromagnetic noise countermeasures were implemented, and Figure 12 (B) is a graph showing the electromagnetic noise measurement results for cartridge 503, an embodiment of this invention. In Figure 12, the dashed-dotted line indicates the FCC standard. The cartridge before countermeasures did not incorporate the above countermeasures (1) to (5), and the upper case 100 and lower case 120 were both made of aluminum. As can be seen from Figure 12, the above countermeasures significantly reduced electromagnetic noise. These countermeasures have been implemented, and cartridges after the countermeasures fully meet FCC standards. C. Modified Cartridge Structure To prevent cartridge theft, the cartridge may be mechanically connected to the printer body. Figure 13 shows an example in which the cartridge 503 is connected to the printer body 1 by 81570. The end of the cartridge 503 has a hole 572 and a ring 573 that passes through this hole 572. One end of the chain 570 is connected to the ring 573, and the other end is screwed to the ground terminal 574 on the printer body 1. Figure 14 shows a cartridge 503 with a locking mechanism using a key 580. When the key 580 is rotated, the protrusion 582 housed inside the cartridge 503 pops out toward the printer body 1 and fits into a groove (not shown) provided in a corresponding portion of the printer body 1. This prevents the cartridge 503 from being pulled out of the printer body 1. The key 580 may also be equipped with a switch function. That is, by rotating the key 580, the cartridge 503 may be locked and powered on. Instead of providing a chain or locking mechanism to prevent theft, the cartridge 503 may be secured by a switch. It may also be screwed to the printer body 1. In the above embodiment, an IC card can be used as expansion memory, but other expansion memory such as an SIMM (Single In-Line Memory Module) may also be used. [ii. Electrical Configuration of the Printer and Cartridge] A. Overall Configuration of the Printer and Cartridge Figure 15 is a block diagram showing the general configuration of the laser printer 500 and the cartridge 503 installed therein that are applied to this embodiment. The laser printer 500 includes an electronic control unit 501 that controls the entire laser printer 500, and a control unit 502 that controls the printing of images on paper P. The laser printer 500 is connected to a workstation 507, and the electronic control unit 501 generates image data (bitmap data) based on print data sent from the workstation 507. The electronic control unit 501 then transfers the image data to the laser engine 505 via a connector CN10. The laser engine 505 then drives the xerography unit 15 to print an image on paper P. As shown in Figure 15, the electronic control unit 1501 includes a well-known CPU (in this embodiment, a Motorola MC68000) 510. The printer includes a ROM 511 that stores programs for printing, a RAM 512 that stores print data and expanded image data, a data input cap 514 that receives print data from the host workstation 505, a line buffer 515 attached to a path line 516 that exchanges data with the cartridge 503, a register 517 that exchanges commands and status information with the laser engine 505, a console panel 1/F 519 that interfaces with the console panel 518 of the laser printer 500, and a double buffer circuit 520 that stores image data to be transferred to the laser engine 505. The double buffer circuit 520 includes two RAMs 520A and 520B, each with a storage capacity of 4 bytes, for eight lines printed by the laser engine 505. The CPU 510 alternately writes image data to these RAMs via a memory write controller 520C. Meanwhile, the laser engine 505 alternately reads data from these two RAMs 520A and 520B via a memory read controller 520D, converting the image data into a video signal in synchronization with the rotation of the photosensitive drum and enabling printing. The reason for alternately writing and reading data to and from the two RAMs 520A and 520B is that access from the CPU 510 and the laser engine 505 must be independent. After writing data to one of the RAMs, the CPU 510 sets a flag in a specified bit of register 517. In response, the laser engine 505 checks this flag and reads the image data stored in the RAM where the data was written. During reading, another bit in register 517 is set to indicate to the CPU 510 which RAM is being read. Since the other RAM is not accessed by the laser engine 505 at this time, the CPU 510 writes the next eight lines of image data to the other RAM. When the laser engine 505 completes reading from one RAM, it resets the flag and switches to reading from the other RAM. The data writing speed from the CPU 510 is faster than the data reading speed from the laser engine 505, i.e., the printing speed, so memory access conflicts between the two are avoided, and the transfer of one page of image data is achieved reliably and easily. Cartridge 503 is connected to the electronic control unit 501 via connector CNII. Line buffer 515 includes a bus driver (not shown) installed along data bus 34. This bus driver is a one-way buffer that transfers data only from connector CNII to CPU 510. In other words, from the perspective of CPU 510, cartridge 503 connected to connector CNII is a read-only device. When electronic control unit 501 is powered on, it determines whether cartridge 503 is attached to connector CNII. If it is, it resets the electronic control unit 501, jumps to a predetermined location in the ROM (described below) stored in cartridge 503, and then sequentially executes the processes stored in cartridge 503. Cartridge 503 interprets programs written in a page description language (PDL) output from workstation 507 to laser printer 500, converts the data into image data, and prints it using laser engine 505. Figure 16 shows the wiring relationship between the plug section 551 formed at one end of the printed circuit board 550 and the connector CNII. The plug section 551 has 25 terminals formed on each of the two sides (side A and side B) of the double-sided printed circuit board. In Figure 16, signal names are listed corresponding to each terminal of the plug section 551. Note that the symbol "/" before the signal name indicates that the signal is low active. The meaning of each signal is as follows: Signal /ASB: Address strobe signal output from the CPU 510 (Motorola MC68000). Signal /UDS: Upper data strobe signal output from the CPU 510. Signal /LDS: Lower data strobe signal output by the CPU 510. Signal /ADS: Address strobe auxiliary signal generated within the electronic control unit 1501 based on the address strobe signal /ASB. This address strobe auxiliary signal /ADS behaves differently for different types of printers when the printer is started up (initialized). In this embodiment, as described below, the printer type is determined based on the behavior of this address strobe auxiliary signal /ADS at initialization. Signal 10DTACK: Output data acknowledge signal when transferring data from cartridge 503 to electronic control unit 501. Signal /CTRGSEL: Cartridge select signal when CPU 510 selects cartridge 503 and accesses ROM, registers, etc. allocated in its internal address space. Signals A1-A20: Address signals output by CPU 510. Signals D1-D15: Output signals from cartridge 503. Signal R/W: Read/write signal output by CPU 510. Signal 5CLK: A clock signal output from an oscillator (not shown) built into laser printer 500. Note that signal /CTRG5 sent to laser printer 500 is pulled low when cartridge 503 is inserted, allowing CPU 510 to detect that cartridge 503 has been inserted into connector CNII. CPU 510 uses 23-bit address signals AI through A23 to specify word addresses, and signals /UDS and /LDS to specify the upper and lower bytes of each word. As a result, CPU 510 can access a 16-Mbyte address space ranging from ooooooohh to FFF FFFh. The symbol rhJ after the address indicates that the address is in hexadecimal notation. B. Cartridge Address Space Cartridge 503 is assigned to a portion of the address space managed by CPU 510 of electronic control unit 501. The CPU 510 handles a 16 MB address space from 00000h to FFFFFFFh, with a portion of this space allocated for the ROM cartridge. The space allocated to the cartridge 503 varies depending on the laser printer model. In the case of a Heeredbacker laser printer, the address space is typically 2 MB, from 200000h to 3FFFFFh or 400000h to 5FFFFFh, as shown in the left column of Figure 17. On the other hand, the microprocessor 601 provided inside the cartridge 503 in this embodiment is an AMD29030-25 MHz microprocessor manufactured by AMD, and its address space is 4 GB, from 00000h to FFFFFFFh. This address space is allocated not only to ROM and RAM, but also to various registers used to exchange data with the printer's electronic control unit 501. This is shown in Figure 18. The electrical configuration within cartridge 503 is described below, along with the address space allocation for both microprocessors. C. Internal Configuration of Cartridge The internal configuration of cartridge 503 is shown in Figure 19. As shown, cartridge 503 is centered around microprocessor 601, which is responsible for overall control. It is broadly composed of memory section 602, consisting of ROM, RAM, and its peripheral circuits; data transfer control section 803, which handles all data exchange with electronic control device 501; and other circuits. Memory section 602 is composed of 2 MB of ROMs 606-609, which store the programs executed by microprocessor 601; selector 610, which switches between banks of ROMs 808-609; and 2 MB of RAMs 611-614, which store print data received from electronic control device 1501 and image data after development. The 2MB ROMs 606 through 609 are each 16-bit x 256K = 4MB mask ROMs, and are assigned addresses from 0 ... ROMs 60B and 607, and ROMs 608 and 609 are assigned the least significant three bits (AO, A1, . All address signals except for bit A2 are input. The two least significant bits (AO, AI) are not input because data is read from microprocessor 601 in 32-bit word units (4-byte units). Furthermore, because address bit A2 is not provided, when reading data from a given area, the four ROMs 606 through 609 output data simultaneously. Data selector 610 sorts the simultaneously output data. Since microprocessor 601 often accesses ROMs at consecutive addresses, two consecutive words (32 bits per word) are read from ROMs 606 through 609 at a time. When consecutive words are actually being read, data selector 610 sequentially switches the banks to which the ROMs belong, reading the data consecutively. This results in extremely fast data output for two consecutive words. On the other hand, RAMs 611 through 614 are 16-bit x 256K = 4M-bit DRAMs, and as shown in II118, are allocated 2M bytes of address space from 20000000h to 201FFFFFh. An additional 2M bytes of memory can be added to cartridge 503, and for this purpose, an expansion RAM interface 615 is provided. This expansion RAM interface 615 is allocated to address space from 20200000h to 203FFFFFFh. Up to 2M bytes of 51MM RAM can be installed in expansion RAM interface 615. The data lines of RAMs 811 through 614 and expansion RAM interface 615 are directly connected to microprocessor 601's data bus DB29, and their address lines are connected to microprocessor 601's address bus AAB via data transfer control unit 603. Note that the I/O addresses of various registers, described below, are allocated starting at 80000000h in the address space. When cartridge 503 is viewed from the electronic control unit 501 of printer 500, the first 128 bytes are allocated to ROM, as shown in the right column of Figure 17. In other words, cartridge 503 also contains a program executed by the CPU 510 of electronic control unit 1501. When cartridge 503 is installed, the CPU 510 of electronic control unit 501 executes a jump command to a specific address in this ROM after completing initialization. Thereafter, the CPU 510 operates according to the processing procedures stored in this ROM. When CPU 510 accesses the first 128 bytes of the 2 MB space allocated to cartridge 503, ROM 618 is accessed by an address signal output via address buffer 617 on cartridge 503's connector-side address bus CAB. The instructions and data stored in ROM 618 are sent to CPU 510 on electronic control unit 501 via data buffer 619 on the connector-side data bus CDH. Note that in Figure 17, "X" indicates the value of the most significant 4 bits of the starting address of the allocated space. D. Explanation of Data Transfer Control Unit 603 In the address map shown in Figure 18, various control and status registers are located at addresses other than those allocated to ROM and RAM. These registers are implemented by data transfer control unit 803, which will be described next. This section focuses on the circuit description, but references will be made to the address map (1117, Figure 8) as appropriate. The data transfer control unit 603 shown in Figure 19 is implemented using a User-Plug 7900 ASIC. This ASIC is a standard cell, model 5SC3630, manufactured by Seiko Epson Corporation, and is a low-power device manufactured using the CMo5 process. The data transfer control unit 803 was designed using the Seiko Epson ASIC Design System rLADSNET, a CAD system. This CAD system provides a library of elements used in logic circuit design, such as latches, flip-flops, counters, and programmable logic arrays. Using these elements, the necessary logic circuit design can be used to automatically generate the ASIC pattern. The data transfer control unit 603, implemented as an ASIC, controls the exchange of data between the CPU 510 of the electronic control unit 501 of the printer 500 and the microprocessor 601 of the cartridge 503 when the cartridge 503 is attached to the connector CNII of the printer 500. Data exchange between the two is achieved by a read control circuit 620 that sends data from the electronic control unit 501 to the cartridge 503 via a read-only data bus, a FIFO control circuit 623 that uses a portion of the same read control circuit 620 to transfer data via a FIFO memory 621, and a double-bank control circuit 624 that enables data prepared by the cartridge 503 to be read from the electronic control unit 501. The FIFO memory 621 is a RAM that stores and reads data in a first-in, first-out order. In this embodiment, a Mitsubishi Electric M6B252FP was used. The data transfer control unit 603 also has an address bus CAB that serves as a signal line to the electronic control unit 501. The data transfer control unit 603 is connected to the address bus CAB via an address buffer 617, and the data bus CDB via a data buffer 619. A first decoder 631 is configured within the data transfer control unit 603, which receives the signal on this address bus CAB and the cartridge select signal C3EL and outputs a selection signal to each unit within the data transfer control unit 603. Similarly, the address bus AAB and control signal CCC from the microprocessor 601 are also connected to the data transfer control unit 603, and a second decoder 632 is configured within the data transfer control unit 603, which receives this address bus AAB and outputs a selection signal to each internal circuit. Furthermore, a second decoder 632 receives this address bus AAB and control signal CCC and outputs a selection signal to each internal circuit within the data transfer control unit 603. A bus control unit 635 is also configured, which outputs address and control signals to RAMs 611 through 814 and expansion RAM interface 615. In addition to these, various registers are configured within the data transfer control unit 603. Reading and writing to these registers is performed by normal read/write operations, and many registers are automatically written when specific processes are performed. The configuration of these special registers will be described later. Furthermore, since cartridge 503 is treated as a dedicated read-only device from the electronic control unit 1501 side, registers that can be written to from the electronic control unit 1501 side are configured to be written by reading from a specified address. In other words, by specifying a specified address, a selection signal is output from first decoder 631, and this signal writes data to the register. Reading from the register is performed by a normal read cycle. Data is read and written from the microprocessor 601 using normal read and write operations. In Figure 49, registers are depicted as connected to a readable bus, with write operations indicated by simple arrows. These registers include an interrupt request register 640, a polling command register 643, a status register (register 511 in Figure 17) 645, a transfer flag register (register 512 in Figure 18) 647, a PROM control register 649, and a control register 650. Of these registers, except for the status register 645 and the transfer flag register 647, these are the collective names for multiple registers assigned as memory addresses 110 to the CPU 510 of the electronic control unit 501 or the microprocessor 601 of the cartridge 503. These multiple registers are not necessarily assigned to consecutive addresses. The interrupt request register 640 has the following registers: 1I Registers AMDINTO, 1, 2 and AMDCLR shown in IJ18 0°1. The polling command register 643 includes the register POLL and the register MC0NTC5. The PROM control register 649 includes the registers EEPCS, EEPSK, and EEPDI. The control register 650 includes the read control circuit 620. This includes all registers not included in the FIFO II circuit 623 and double bank control circuit 624, but not listed above. These are the registers ADDMUXA, ADDMUXB, CLKDIV, RTCVAL, and RTCON shown in Figures 171 and 18. RTCSEL, RTCCLR, and 5YSKEEP. Also, among the 512-byte areas shown in Figures 171 and 18, EWWRL and EWWRH are accessed from the electronic control unit 501 by the first and second latches 651 and 652 of the read control circuit 620. 17 is an area used for writing data to FIFO memory 621, and register EWRD corresponds to latches 851 and 852 as one word, as viewed from the microprocessor 601 side. Registers FIFOREQ, FIFOR9T, and FIFOWR correspond to FIFO register 653 of FIFO control circuit 623, and registers F1RCLK, RDCLK, FIFORD, and RDRST correspond to FIFO read register 655 of FIFO control circuit 623. The FIFO1111 circuit 623 also includes a latch 657 that holds data to be written to FIFO memory 621 using part of the read control circuit 620's functions. The areas indicated by symbols DPRAMA and DPRAMB in FIG. 17 are buffers with a capacity of 32 bytes, and are the first and second registers of double bank control circuit 624. Second buffer 6 58. 659 as seen from the electronic control unit 1501 side. This buffer 858. 659 as seen from the microprocessor 601 side are the banks DPWROA and DPWROB shown in Figure 18. Note that certain bits di and d2 of the status register 645 are also used to exchange data via the double bank control circuit 624; details of these will be discussed later. E. Description of Registers The interrupt request register 640 generates and holds interrupt requests from the electronic control unit 1501 to the microprocessor 601. Three levels of interrupts from the electronic control unit 501 to the microprocessor 601 are available, and as shown in Figure 17, three registers (AMDINTO, 1, and 2) are provided. Reading any of the interrupt request registers 640 from the electronic control bag @501ffi generates an interrupt request to the microprocessor 601. This register is set by a read operation from the electronic control unit 501, but the read data is meaningless and is unrelated to the generation of the interrupt request. A specific example of the configuration of this interrupt request register 640 is shown in Figure 23. These registers are composed of D-type flip-flops, and when the electronic control 811! 501 reads the registers, the first decoder 631 outputs the signal /AMDINTO,1,2, which sets the output terminal Q of each flip-flop 640a+b+c to active low, outputting the interrupt signal /INTO,1,2. Note that the symbol "/" before the signal indicates that the signal is low active (the same applies below). The registers that clear the outputs of these flip-flops 640a+b+c are three read-only registers (AMDCLRo,1.2), as shown in Figure 18. 2) are assigned to specific addresses. Therefore, when microprocessor 601 performs a read operation on each address assigned to this register, second decoder 632 outputs signals /INTCLR0, 1, and 2, respectively, and the corresponding flip-flops are preset. To issue an interrupt request from electronic control unit 501, it simply accesses one of interrupt request registers 640, and microprocessor 601 determines the priority and processes the interrupt request accordingly. In this case, microprocessor 601 clears the corresponding interrupt request register 640a, 640b, or 640c. Signals beginning with "rPUP," such as signal PUP2, are output from reset signal output circuit 637 and go low upon reset, etc. Signal PUP2 shown in Figure 23 is a signal for clearing three interrupt requests at once. The polling command register 643 is a register that passes commands from the microprocessor 801 (II) to the electronic control device 501. It is a register that can be written to by the microprocessor 601 (II) and read from the electronic control device 501. An example of the hardware configuration of this register is shown in Figure 20. As shown, the polling command register 643 can be composed of two off-type D flip-flops 643a*b and one D flip-flop 643c, which form a 16-bit data latch. The data input terminals ID through D of the off-type D flip-flops 843a,b are connected to the data bus DB29 (16-bit bus width) from the microprocessor 601. The output terminals IQ through IQ are connected to the data bus DB88 (16-bit bus width) from the electronic side ALL device 501611. The clock terminal CK of the offal D all flip-flops 643a, b is connected to the signal /MC0NTCS output from the second decoder 632 when the polling command register 643 is accessed from the microprocessor 601 (Figure 18, register MC0NTCS). When this signal goes active low, the contents of the data bus DB29 on the microprocessor 601 side are latched into the offal D all flip-flops 643a, b. The output enable terminal OE, which enables the output of the offal D all flip-flops 643a, b, is connected to the electronic control When polling command register 643 is accessed from device 501 (FIG. 17, register POLL), signal /POLL is output from first decoder 631. When this signal goes active low, the data held in off-type D flip-flops 843a, b is output to data bus DB68 on the electronic control device 501 side. Signals /MC0NTC5 and /POLL are connected to clock terminal C and preset terminal PR of D-type flip-flop 643c. Signal CMDRD from output terminal Q is set high when data is latched by off-type D flip-flops 643a, b (signal /MC0NTC5 goes low), and this data is sent to the electronic control device 501 side. When read from the electronic control unit 501 (signal /POLL is low), it is reset to a low level. The output signal CMDRD of D-type flip-flop 643C is a specific bit d3 (hereinafter referred to as flag CMDRD) of status register 645 that can be output from the electronic control unit 1501. Therefore, by reading this status register 645 from the electronic control unit 1501, the electronic control unit 111j11501 can know that a command has been set in the polling command register 643 from the microprocessor 601. When the electronic control unit 501 sees flag CMDRD, bit d3 of status register 645, and learns that a command has been set, it executes the polling command through a normal read cycle. The microprocessor 601 reads the contents of the polling command register 643, i.e., the command sent from the microprocessor 601. The command contents include an instruction to start transferring print data to the data transfer control unit 603, an instruction to start printing, or a message to display on the console panel 518. When the electronic control unit 501 reads the contents of the polling command register 643, as shown in FIG. 20, the output signal CMDRD of the D-type flip-flop 643c is inverted to high level by the signal /POLL. Therefore, by monitoring a specific bit d2 of this transfer flag register 647, the microprocessor 601 can determine whether the command it output has been read by the electronic control unit 1501. The status register 645 is This register holds the information shown in FIG. 21, in addition to the information indicating whether a command has been set from the microprocessor 601. The contents of each bit will be explained below. Bit d0 is set low by a signal EWRDY generated within the continuous output control circuit 620 when data is written from the electronic control unit 501 (described later). When that data is read by the microprocessor 601, it is reset high by a signal from the second decoder 632. This bit is called flag EWRDY. Bits d1 and d2 indicate whether the double bank control circuit 624 is accessible from the electronic control unit 1501 or the microprocessor 601, respectively. These flags are called ADDMUXA and ADDMUXB. Two bits correspond to each of the two transfer banks built into the double bank control circuit 624. These bits d1 and d2 are set or reset by the microprocessor 601 writing data to bit d0 of register ADDMUXA or ADDMUXAB included in the control register 650, as shown in FIG. 18. Therefore, the microprocessor 601 sets this flag to a low level before writing data to one bank of the double bank control circuit 624, and resets it to a high level after the write is complete. If the electronic control unit 501 reads data from the bank where this flag is high, data will be transferred alternately to the two banks. By writing and reading data, data can be continuously transferred from the microprocessor 601 to the electronic control unit ml501. Bit d3 (flag CMDRD) has already been described. Bit d5 is flag CLKDIV, which is set based on the microprocessor 601's operating clock. The microprocessor 601's operating clock is the clock CLK output from the first oscillator 661 using an external crystal oscillator CRC1. However, when the microprocessor 601 writes a value of 0 to a specific bit dO of register CLKDIV in control register 650, the microprocessor 601's operating clock CLK becomes 25 MHz. Writing a value of 1 to bit dO sets the operating clock CLK to 12. 5 MHz. Status flag CLKDIV in register 645 from the perspective of electronic control unit 501 is set to a low level when this clock CLK is 25 MHz, and 12. This bit is set high when the microprocessor 801 is in sleep mode. When the electronic control unit 501 needs to know the operating clock frequency of the microprocessor 801, i.e., its operating speed, to synchronize data transfer timing, it checks this bit in the status register 645. Bit d6 is a flag, ADMON, that is set high when the microprocessor 601 is operating and set low when it enters sleep mode. In this embodiment, the microprocessor 601 receives page description language (PDL) data from the electronic control unit 501 and expands it to image data. Therefore, if a predetermined time has passed without receiving any PDL data to be processed from the electronic control unit 501, the microprocessor 601 will initially reduce its operating frequency to 172, i.e., 12.5M, to conserve power. 5 MHz, and after a certain amount of time has elapsed, it stops its operation and enters sleep mode. At this time, microprocessor 601 writes a value of 0 to register ADMON in control register 650. As a result, bit d6 of status register 645 goes low from the perspective of electronic control device 1501. By checking this bit, electronic control device 601 can determine the operating mode of microprocessor 601. Note that a real-time clock built into data transfer control unit 603 is used to measure time, etc. This real-time clock clock, RCLK, is generated by a second oscillator 667 constructed using an external crystal oscillator 665. The real-time clock is configured within bus control unit 635 and receives instructions from microprocessor 601 to measure the passage of a predetermined period of time. The crystal oscillator and oscillator are connected to each other. The purpose of the PROM control register 649 is to allow the microprocessor 601's operating clock CLK to be changed independently of the real-time clock's operating clock RCLK. The real-time clock can specify a 4N-type interval timer by setting the d1 bit of registers RTCVAL and RTCSEL, which belong to the control register 650, low or high. The timer can be started by writing a value of 1 to a specified bit dO of register RTCON. Once started, the timer outputs an interrupt request signal to the microprocessor 801 at specified intervals until it is stopped by writing a value of 0 to bit do of register RTCON. Upon receiving this interrupt request signal, the microprocessor 601 reads register RTCCLR and clears the interrupt request. The output of these interval timers is used to count user time and other events in page description language processing. Next, the configuration of the PROM control register 649 will be described. PROM control register 649 includes registers EEPC5, EEPSK, and EEPDI (see Figure 18). These registers are used to exchange data with EEPROM 670, an electrically erasable and rewritable memory built into cartridge 503. In this embodiment, cartridge 503 stores various variables (configuration variables) necessary for the operation of laser printer 500 in EEPROM 870. This EEPROM 670 is a type that reads, erases, and writes data via serial transfer. In this embodiment, an NMC93C68X3 manufactured by NAS Semiconductor Corporation is used. This EEPROM 670 has a storage capacity of 16 bits x 256 bytes (number of registers) and can read, erase, and write the contents of any specified register. When EEPROM 670 is selected by chip select signal C3, it receives data "C" sent to serial data input terminal Din in synchronization with serial data clock SL. The first three bits of the data transfer are interpreted as a command to the EEPROM, and the next eight bits are interpreted as the register number to which data is to be read, erased, or written. When writing data, following these commands and register designation, the data to be stored is applied to data input terminal Din in synchronization with serial data clock SL. Register EEPC5 switches the chip select signal; when microprocessor 601 writes a value of 1 to bit dO of this register, EEPROM 670 is selected. Register EEPSK is a register that generates the serial data clock SK. Microprocessor 801 generates the serial data clock for EEPROM 670 by alternately writing the value 0 and the value 1 to this register. Register EEPDI is a register that holds one bit of data to be written to EEPROM 870. In synchronization with rewriting register EEPSK to generate serial data clock SK, microprocessor 601 rewrites a specific bit dO of register EEPDI according to the data to be written. The data output terminal Dout of EEPROM 670 is a specific bit dO of the transfer flag register 647 described above. Microprocessor 601 outputs a data read command and the number of the register to be read to EEPROM 870, and then reads bit dO of transfer flag register 647 in synchronization with serial data clock SK to read the contents of the specified register. The data stored in EEPROM 870 is preserved even when the power is turned off. The contents of EEPROM 870 can be read immediately after powering on the laser printer 500, restoring the configuration to the state it was in immediately before power was turned off. F. Configuration and Function of the Readout Control Circuit 820 Next, we will explain an example configuration of the readout control circuit 620 and the procedure for data transfer by the readout control circuit 620. The readout control circuit 620 reads ε (pi-bit) x 2 first. Second latch 651. 652, and ROM 871, which outputs the data necessary for transfer, as shown in FI! J22. It also includes a D-type flip-flop 674 that generates the EWRDY flag (bit do) of the status register 645, a counter gate 672, and a status register 645. When viewed from the electronic control unit E501 side, the output control circuit 620 includes this latch 651. 652 corresponds to the two registers EWWRL and EWWRH, which transfer data in 8-bit units, as shown in Figure 17. These registers are used to transfer the lower and upper bytes of one word (16 bits) of data. Second latch 651. When viewed from the microprocessor 601 side, 652 corresponds to the register EWRD shown in FIG. 18. That is, the microprocessor 801111 transmits data to both latches 6521 and 6522 via the data bus DB290. 652 can be read as one word. The ROM 671 of the read control circuit 620 is a ROM that stores 256 bytes of data and can be implemented, for example, using fuse ROM or a small-capacity FROM. Of course, it can also be implemented as part of a larger-capacity ROM. If RAM is used, equivalent functionality can be achieved by transferring data in advance. The address terminals AO through NUA7 of this ROM 671 are connected to the lower 8 bits (Act through AC8) of the address lines from the connector-side address bus CAB, and the data terminals OO through OO7 are connected to the inputs ID through ID8D of the first latch 851 and the second latch 652. The output of ROM 871 is also output to the FIFO control circuit 623 as data buses ZO through Z7 for the FIFO control circuit 623. First latch 651. The output of second latch 652 is connected to data bus DB29 and can be read by microprocessor 601 as register EWRD. The output signal /EWROM of triplet gate 672 is input to chip select CE and output enable OE of ROM 671. When any of the signals /EWWRH, /FIFORWARD, or /EWWRL input to triplet gate 672 goes active low, ROM 671 outputs data from the address specified by the lower 8 bits of connector-side address bus CAH. Signal /EWWRH goes low when the read control circuit 620 specifies the transfer of the upper byte. Signal /EWWRL goes low when the read control circuit 620 specifies the transfer of the lower byte. Signal /FIFOR goes low when the FIFO control circuit 623 specifies the data transfer. Signals /EWWRL and /EWWRH are input to the clock terminals CK of the first latch 651 and the second latch 652, respectively. Therefore, when these signals become active and data is output from ROM 671, the data is read from the first latch 651. The signal EWRDY is held in the second latch 652. Furthermore, since the signal d/EWRRL is also input to the clock terminal C of the D-type flip-flop 674, when the lower byte is transferred, the output Q of the D-type flip-flop 674 is inverted to a low level. This output EWRDY is treated as the bit dO of the status register 645 and bit d1 of the transfer flag register 647, i.e., the flag EWRDY. First latch 651. The second latch 652 is treated as the register EWRD by the microprocessor 601. Therefore, when attempting to read data stored in the first latch 51 and the second latch 52, the microprocessor 601 performs a read operation on the register EWRD. At this time, the signal /EWRD becomes active low, and this signal is transmitted to the first latch 651 connected to the output enable terminal. The previously held data is output to the output of second latch 652, i.e., data bus DB29. This signal /EWRD is connected to preset terminal PR of Off flip-flop 674, so that as soon as the data in first latch 651 and second latch 652 is read from microprocessor 601, signal EWRDY, the Q output of D-type flip-flop 674, is inverted to a high level. In other words, bit d0 of status register 645 and flag EWRDY, which is bit d1 of transfer flag register 647, are set to a value of 1. Based on this hardware configuration, electronic control unit 501 and microprocessor 601 transfer data from electronic control unit 11501 to microprocessor 601 in the following manner: The data transferred from the electronic control device 501 to the microprocessor 601 is print data received by the electronic control device 501 from the workstation 507, and is a page description language program to be processed by the microprocessor 601 of the cartridge 503. Data transfer by the read control circuit 620 is performed by the data transfer processing routine to the cartridge (FIG. 24) executed by the CPU 510 of the electronic control device 501, and the data read interrupt processing routine (1m26) executed by the microprocessor 601 of the cartridge 503. Once the print data to be transferred to the cartridge 503 is ready, the CPU 510 initiates the process shown in the flowchart of FIG. 24, first reading the EWRDY flag (bit do) of the status register 645 (step 5700). This EWRDY flag is stored in the first latch 651 of the read control circuit 620. When data is set in the second latch 652, it becomes 0, and when the data is read by the microprocessor 601, it is set to 1. Next, a determination is made as to whether the EWRDY flag is 1 (step 3705). The microprocessor waits until the EWRDY flag becomes 1. If it does, it then reads the address of (the starting address of area EWWRH + the data D to be transferred x 2) (step 5710). When a read operation is performed on area EWWRH, data is read from ROM 671. As shown in FIG. 25, 256 pieces of data, from 00h to FFh, are written sequentially to even-numbered addresses starting from the starting address EWWRH in ROM 671. Data is not placed at odd addresses because CPU 510 typically accesses data in single words (16 bits), and word-by-word access starting from an odd address is not possible (this would result in an address bus error). When a read operation is performed on an address DX2 away from the beginning of area EWWRH, data D is read from ROM 671 and latched in second latch 652, as shown in FIG. 22. After the upper byte of the data to be transferred has been transferred (second latch 652 holds the data), CPU 510 similarly transfers the lower byte (first latch 651 holds the data) (step 5715). Through the above process, one word's worth of data is stored in the first latch 652. Second latch 651 . Assuming that the data is held in first latch 652, CPU 510 sets one of the interrupt request registers (AMDINTO in this embodiment) (step 5720). CPU 510 then repeatedly executes the transfer processing routine shown in FIG. 24. However, once the data is held in first latch 651, as shown in FIG. 22, flag EWRDY is set low. Therefore, the next data transfer process is not performed until flag EWRDY becomes high (value 1) (step 8700). 705). When the CPU 510 sets the interrupt request register (AMDINTO), the microprocessor 601 accepts this interrupt request and initiates the data read interrupt processing routine shown in Figure 26. This processing is initiated by the first. Immediately after the data is held in the second latches 851 and 652, microprocessor 601 reads register EWRD to read one word of data prepared by electronic control unit 501 (step 5730). Microprocessor 601 then transfers this data to a designated area in RAM 611 through 614 (step 5735). Through the above-described process, electronic control unit 1501 can transfer data to cartridge 503, which is only connected via data bus CDB, a dedicated line. Furthermore, since data is written in bytes and read in words, microprocessor 601 can efficiently retrieve data. While the example shown here illustrates the transfer of one word of data, data transfer does not have to be in words; it can also be in bytes. In this case, transfers are performed only using the EWWRL area, and microprocessor 801 discards the upper 8 bits of data. G. Configuration and Function of FIFO Control Circuit 623 FIFO control circuit 623 includes a latch 657 that latches data to be written to FIFO memory 621, a FIFO write register 653 that controls the writing of data to this FIFO memory 621, and a FIFO read register 655 that also controls the read/write operation. This FIFO memory 621 It can store 1,152 bytes of data and is equipped with an internal write address counter and a read counter. FIFO memory 621 is equipped with a write reset terminal and a read reset terminal for resetting these counters, respectively, an 8-bit write data bus, an 8-bit read data bus, a write clock terminal, and a read clock terminal. To transfer data from electronic control device 501m to microprocessor 601 using this FIFO memory 621, CPU 510 of electronic control bag 501 executes the transfer processing routine shown in Figure 27, and microprocessor 601 of cartridge 503 executes the processing routine shown in Figure 28. First, the processing routine shown in the flowchart of Figure 27 will be explained. Electronic device 11b Transferring multiple bytes of data When the CPU 510 of the electronic control unit 501 initiates the data transfer processing routine shown in Figure 27, it first reads register PIFOR5T belonging to the FIFO write circuit 654 of the FIFO control circuit 623 and resets the write-side address counter (step 5750). Next, it resets variable N to the value 0 to count the number of data items to be sent (step 5755). It then reads the address (the starting address of register FIFOWR + the data DX2 to be transferred) (step 8780). Reading this address accesses a specific address in ROM 671 (see J25), just as with the control circuit 620, and outputs the data D that the CPU 510 intended to transfer. This data is then stored in latch 657 via buses ZO through Z7 shown in Figure 22. The data D held in latch 657 is then latched by the FIFO control circuit 623. Next, register FIFOREQ of the FIFO control circuit 623 is read, and data D held in latch 657 is transferred to the FIFO memory 621 (step 5765). Reading register FIFOREQ outputs a write clock to the write-side clock terminal of FIFO memory 621, and data D held in latch 657 is written to the address indicated by the write-side address counter of FIFO memory 621. At the same time, the contents of the write-side address counter in FIFO memory 621 are incremented by 1. After writing one byte of data in this way, variable N, which indicates the number of transferred data, is incremented by 1 (step 5770), and a determination is made as to whether variable N is equal to the total number of bytes X of data to be transferred (step 5775). Therefore, the above-described processing of steps 5760 through 5775 is repeated until the transferred data bytes @N equals the total number of data bytes X. When all data transfers are complete, the CPU 510 sets one of the interrupt request registers (AMDINT1), notifies the microprocessor 601 that the data transfer is complete (step 5780), and exits to rNEXTJ, terminating this processing routine. Meanwhile, upon receiving this interrupt request AMDINT1, the microprocessor 601 initiates the data receive interrupt routine, the flowchart of which is shown in Figure 28. Upon initiating this routine, the microprocessor 601 first reads register RDR8T, which belongs to the FIFO read register 655 of the FIFO control circuit 623, and resets the address counter on the read side of the FIFO memory 821 (step 5800). Next, the microprocessor 601 sets the value of variable M, which counts the number of received data, to 0 (step 5805). Next, the register FIRCLK' belonging to the FIFO read register 655 is read (step 5810), and the read data is transferred to a specified area in RAM 811 or 614 (step 5815). When register FIRCLK is read, a read clock is output to the read-side clock terminal of FIFO memory 621, and data D from the address indicated by the current read-side address counter is read. At the same time, the contents of the read-side address counter in FIFO memory 621 are incremented by one. Note that, since what is typically transferred via FIFO memory circuit 623 is a page description language program, the received data is immediately transferred to the RAM area and prepared for image data development. When one byte of data is received, the variable M is incremented by one (step 5820), and a determination is made as to whether this variable M is equal to the total number of bytes of data to be transferred, X (step 5825). Therefore, steps 5810 through 5825 are repeated until the number of bytes of received data, M, matches the total number of bytes of data, X. When it is determined that all data has been received, the microprocessor 601 writes a command indicating completion of data reading to the polling command register 643 (step 5630). By reading the contents of this polling command register 643, the CPU 510 on the electronic control unit 501 can determine that data reception by the FIFO control circuit 623 has been completed. The microprocessor 601 then exits to rRNTJ and terminates this processing routine. The above-described processing enables efficient transfer of large amounts of data from the electronic control unit 501 to the microprocessor 601. The transferred data is stored in a designated area of RAM 611-614 of data transfer control unit 603 and awaits processing by microprocessor 601. When microprocessor 601 receives all print data (a program written in a page description language) to be rendered from electronic control unit 1501, it activates the page description language interpreter stored in ROM 606-608 and processes the print data stored in a designated area of RAM 611-614. This processing renders the image, and the rendered results are stored as image data in a designated area of RAM 611-614. H. Configuration and Function of Double Bank Control Circuit 624: The image data obtained after rendering is then transferred to electronic control unit 1501, stored in RAM 612, and printed by laser engine 505 at the designated timing. The double bank control circuit 624 performs this image data transfer. The double bank control circuit 624 transfers data from the microprocessor 801m to the electronic side device 50161 and has two sets of banks that store 32 bytes (16 words) of data. These are called Bank A and Bank B, but since the hardware is identical, only an example of the configuration of Bank A is shown in Figure 29. Each bank is configured so that its address and data bus can be switched between the microprocessor 601m and the electronic side 601m. As shown, data selectors 681, 682 select the address line. Four off-line buffers 684 to 687, used in pairs to select the data bus (16 bits wide). RAM with 32 bytes of storage capacity 891. The microprocessor 601 is composed of a RAM 692, and other gates, OR gates 694, 695, and inverter 696. The rEJ29 uses two memory chips with a storage capacity of 32 bytes, but this can also be achieved by switching the upper address of a single memory chip. Data selector 68 selects and outputs the least significant four bits (AC1 through AC4) of the address bus CAB of the electronic control unit ff1501111 and the least significant four bits (A2 through A5) of the address bus AAB of the microprocessor 601. The address bus is selected by the ADD MUXA signal (bit do of register ADDMUXA) connected to select terminal S. Data selector 682 selects RAM 691. in accordance with the address bus selection. The ADDMUXA signal connected to the same select terminal S switches the read and write signals of RAM 691, 692. Either signal is connected to the chip select terminals CE1, CE2, CE3, CE4, CE5, CE6, CE7, CE8, CE9, CE10, CE11, CE22, CE33, CE34, CE35, CE36, CE37, CE38, CE39, CE40, CE41, CE42, CE43, CE44, CE45, CE46, CE47, CE48, CE49, CE41, CE42 ... 2. Switches whether or not it is connected to the output enable terminal OE. Ophthalmic line buffer y884. 685 is a tri-state type line buffer connected to data bus DB29. When gate terminals IG and 2G go low, the data bus DB29 on the microprocessor 601 side and RAM89 1. 692 data bus is connected to the microprocessor 601 ([1 to RAM 891. 692. Ophthalmic Line Buffer 684. The output of OR gate 694, which receives signals /DPWROA and ADD MUXA, is connected to gate terminals IG and 2G of 885. Signal /DPWROA goes low when microprocessor 601 attempts to write data to bank A. Therefore, if bit dO of register ADDMUXA is set low beforehand to write data to bank A, then when microprocessor 601 attempts to write data to bank A, offal line buffer 684. The gate of 685 opens, and the data output to data bus DB29 is output to the data buses of RAMs 691 and 692 and written thereto. On the other hand, when the gate terminals IG and IG of ophthalmic line buffers 68B' and 687 go low, they connect data bus DB88 on the electronic control 811501 side to the data buses of RAMs 691 and 692, thereby disabling RAM 691. Data can now be read from 692 to electronic control unit 1501. The gate terminals IG and 2G of ophthalmic line buffers 686 and 687 are connected to the output of OR gate 695, which receives signal /DPOEIA and signal ADDMUXA inverted by inverter 696. Signal /DPOEIA goes low when electronic control unit 501 attempts to read data from Bank A. Therefore, if bit dO of register ADDMUXA is set high in advance to read data from Bank A, when electronic control unit 501 performs a continuous data transfer operation on Bank A, the gates of ophthalmic line buffers 886 and 887 open, and the data output to the data bus of RAM 691 and 692 is output to data bus DB68. Based on this hardware configuration, we will now explain the image data transfer process performed by microprocessor 601 and the reception process performed by CPU 510 of electronic control device 501. Figure 30 is a flowchart showing the image data transfer start processing routine performed by microprocessor 601. As shown, prior to transferring image data, microprocessor 601 sets a transfer start command in polling command register 643 (step 5850). The CPU 510 of electronic control device 501 reads the command in polling command register 643 and executes the response processing routine shown in Figure 31. That is, electronic control unit 501 determines whether laser printer 500 is ready to print (step 5880). If so, it sets one of the interrupt request registers (AMDINT2) (step 5865) and exits to rNEXTJ, temporarily terminating this routine. If laser printer 500 is not ready to print, it notifies microprocessor 601 of cartridge 503 (step 5870). An inability to print refers to a situation in which printing is not possible even when image data is transferred, such as when laser engine 505 has not yet warmed up or a paper jam has occurred. Upon receiving interrupt request signal AMDINT2 from electronic control unit 501, microprocessor 601 initiates the image data transfer interrupt processing routine shown in FIG. 32. When this process is initiated, the microprocessor 601 first writes a value of 1 to bit dO of register ADDMUXA (step 5900). If bit dO of register ADDMUXA is set to a value of 1, then, as explained using FIG. 29, RAM 691., which constitutes bank A, is written to the RAM 691. The data bus of 692 is connected to the data bus DB29 on the microprocessor 601 side, and access from the electronic control unit 1501 side is disabled. Next, microprocessor 601 transfers 16 words (32 bytes) of data to bank A DPWROA (step 5902). After writing the data to bank A DPWROA, signal /DPWROA shown in FIG. 29 goes low, and off-chip line buffer 884. Data is sent to RAM 691 via 685. 692. Upon completion of the 16-word data transfer, microprocessor 801 writes the value 1 to bit dO of register ADDMUXA (step 5904) and connects the data bus of RAMs 691 and 892 constituting Bank A to data bus DB68 of electronic control unit 501. Microprocessor 601 then writes command data to polling command register 643 indicating the completion of the transfer to Bank A (step 5908). This completes the data transfer to Bank A, and microprocessor 601 then executes the same process as described above for Bank B (step 5910). When the data transfer to Bank B is complete, microprocessor 601 writes command data to polling command register 643 indicating the transfer is complete. This completes the transfer of a total of 32 words (64 bytes) of data from cartridge 503 to Banks A and B. In response to the processing of microprocessor 601 described above, CPU 510 of electronic control bag 1501 executes the image data reception processing routine shown in FIG. 33. That is, CPU 510 first reads bit d3 of status register 645, i.e., flag CMDRD (step 5920), and determines whether it is set to the value 0 (step 5925). If command data is written to polling command register 643 from microprocessor 601, flag CMDRD is set to the value 0. At this time, CPU 510 reads the command data from polling command register 643 (step 5930). The read command data is then checked to determine whether it indicates that data transfer from bank A has been completed (step 5935). If not, other processing is performed (step 5940). If the command data in polling command register 643 indicates that the data transfer for bank A is complete, electronic control unit 1501 reads 16 words from bank A DPRAMA (see Figure 17) (step 5945) and transfers the read data to RAM 512 (step 5950). Since the above process completes the reading of 16 words of data from bank A, electronic control unit 501 sets one of the interrupt request registers (AMDINT2) to allow microprocessor 801 to transfer the next 16 words. Next, steps 5920 through 5955 described above are executed for bank B. That is, when the microprocessor 601 determines from the command data in the polling command register 643 that the data transfer from bank B to bank B is complete, it reads 16 words of data from bank B DPRAMB and transfers them to RAM 512. It then sets one of the interrupt request registers to issue an interrupt request to microprocessor 601. Upon receiving this interrupt request, microprocessor 601 re-executes the interrupt processing routine shown in FIG. 32. Therefore, the transfer of all image data is completed when microprocessor 601 and CPU 510 execute both routines (FIGS. 32 and 33). If no new print data is received from electronic control unit 501 after the transfer of all image data, microprocessor 601, after a predetermined time has elapsed, writes a value of 1 to register CLKDIV in control register 650 and halves its operating frequency to 12. 5 MHz, reducing power consumption and heat generation. Printing Image Data Meanwhile, the electronic side mam 50t, which has received all the image data, prints the image data while exchanging signals with the laser engine 505 using the double buffer circuit 520 and register 517 described above. Figure 34 shows a simplified diagram of the signal exchange between the electronic control unit 501 and the laser engine 505. Referring to this diagram, we will explain the printing overview. Upon receiving image data extracted from the cartridge 503, the electronic control unit 1501 inquires whether the laser engine 505 is ready to print. If it determines that warm-up and other procedures are complete and the laser engine 505 is ready to print, it outputs the print signal shown in Figure 34 to the laser engine 505 via register 517. Upon receiving this signal, the laser engine 505 immediately starts the paper feed motor. Synchronously, photosensitive drum rotation, charging, and other processes begin. When the paper to be printed reaches a position a predetermined distance away from the photosensitive drum, laser engine 505 detects the leading edge of the paper and outputs signal VREQ to electronic control unit 501 via register 517. Upon receiving signal VREQ, electronic control unit 501 waits a predetermined time, i.e., the time required for the photosensitive drum to rotate to a position where latent image formation by the laser beam begins, and then outputs signal VSYNC via register 517. Upon receiving signal VSYNC, laser engine 505 outputs a horizontal synchronization signal (ISYNC) for the laser beam via register 517. Since signal HSYNC corresponds to a signal instructing the start of reading one line of image data, laser engine 505 synchronizes with this signal and reads the image data from one of RAMs 520A or 520B of double buffer circuit 520. When forming a top margin, the VSYNC signal is ignored for the number of lines corresponding to the top margin. This control is also performed when forming a bottom margin. At the same time, CPU 510 counts this signal and transfers the necessary image data to RAM 520A or RAM 520B of double buffer circuit 520. A predetermined amount of time has passed since laser engine 505 detected the trailing edge of the paper, and when the horizontal synchronization signal value becomes equal to a value preset according to the paper size, CPU 510 terminates the transfer of image data to double buffer circuit 520. Through the above process, one page's worth of image data is transferred to laser engine 505, and the image is printed on the paper. [iii. Other (1) While the above describes an embodiment in which the present invention is applied to a printer, the present invention is not limited to printers; it can also be applied to, for example, word processors, personal computers, and workstations. In recent years, such computer-related devices often have expansion slots and the ability to accommodate cartridge-type expansion devices such as IC cards. In such word processors, personal computers, etc., equipped with expansion slots or IC cards, the cartridge of the present invention can be inserted and the processing of the main processor can be transferred to processing stored in the cartridge's built-in memory using monitor commands, etc., and information can be processed together with the cartridge's processor. This makes it easy to improve, add, or change information processing functions. Furthermore, since the processing content can be changed in any way once control is transferred to the cartridge, it is possible to easily change the processing content of already sold devices. This allows for the modification or improvement of functions, as well as the upgrading of software in various dedicated devices such as word processors. In this way, the present invention can be applied to cartridges for any processor-based device, such as in-vehicle electrical equipment, facsimiles, telephones, electronic organizers, electronic musical instruments, electronic cameras, translators, handy copiers, cash dispensers, remote control devices, and calculators, and any other information processing device that can be connected via a connector. In such information processing devices, if the main processor has the ability to recognize the cartridge and transfer its processing to an address prepared on the cartridge, it is easy to implement the cartridge of the present invention in existing electronic devices. Even if such functionality is not provided, various methods can be considered for transferring the main processor to processing stored on the cartridge. When reading data from a specified address, esooo-based processors check whether data is established on the data bus. The output device (slave) determines whether or not a jump instruction to an absolute address is being executed based on a DTACK signal sent back to the processor. Therefore, when the mainframe's processor attempts to execute a jump instruction to an absolute address while executing a process stored in the mainframe's ROM, the cartridge analyzes the instruction and detects that the jump instruction is to an absolute address. Then, before the mainframe's ROM outputs the absolute address of the jump destination to the data bus, the cartridge's built-in ROM's execution address is output to the data bus and a DTACK signal is returned to the mainframe's processor, forcing the process to proceed to a specified address within the cartridge. Once the process has been transferred to the cartridge's ROM, subsequent processing can be configured in any way. While this example assumes that the mainframe's processor executes a jump instruction to an absolute address, it is important to note that the jump instruction itself is also generated from the mainframe's ROM. However, when the instruction scene is first read from ROM after power-on, it is also possible to configure the cartridge to place a code equivalent to a jump command on the data bus and return a DTACK signal prior to reading the instruction scene. While these approaches may result in DTACK signal contention, they are feasible with careful analysis of bus timing. (2) The present invention is not limited to the above embodiments. It goes without saying that various embodiments within the scope of the present invention may be implemented, such as a cartridge with a built-in outline focus receiving data such as character point size from the printer, generating a bit image of the character at a specified point size, and transmitting it to the printer; a cartridge simply storing and displaying data received from an electronic device without any particularly complex processing; or a printer in which the printer is an inkjet printer.

[Industrial Applicability]

The electronic device cartridge of this invention can be used in any processor-based device, such as word processors, personal computers, workstations, automotive electronics, fax machines, telephones, electronic organizers, electronic musical instruments, electronic cameras, translators, handheld copiers, cash dispensers, remote control devices, and calculators, as well as any other information processing device that can be connected via a connector.

Claims (30)

[Claims] 1. An electronic device cartridge that is inserted through a predetermined insertion port into an electronic device having a first processor capable of logical operations, the electronic device cartridge comprising: a conductive shielding member; and connecting means for electrically connecting the shielding member to a conductive member of the electronic device. 2. The cartridge for an electronic device according to claim 1, further comprising a second processor and a circuit board on which the second processor is mounted, wherein the connecting means comprises means for electrically connecting the shielding member, power supply wiring on the circuit board, and conductive members of the electronic device. 3. The cartridge for an electronic device according to claim 2, further comprising a housing for accommodating the substrate, the housing including the shielding member. 4. The cartridge for an electronic device according to claim 3, wherein at least a portion of the housing is made of metal. 5. The cartridge for an electronic device according to claim 3, wherein at least a portion of the housing has a conductive layer. 6. A cartridge for an electronic device according to claim 3, wherein the housing comprises first and second housing elements that fit together to house the substrate, and wherein a conductive layer is formed on the mating surfaces of the first and second housing elements at least in the protruding portions of the cartridge that protrude from the electronic device when the cartridge is inserted into the electronic device. 7. The electronic device cartridge of claim 6, wherein one of the first and second housing elements is made of plastic and the other is made of metal. 8. The electronic device cartridge according to claim 2, wherein the connecting means electrically connects the power supply wiring of the circuit board and the shielding member at a plurality of locations. 9. An electronic device cartridge according to claim 3, wherein the housing has a through-hole, and the connection means further includes means for electrically connecting the power supply wiring of the circuit board to the shielding member at at least one location between both ends of the through-hole. 10. The cartridge for an electronic device according to claim 3, wherein the connecting means comprises a conductive elastic member fixed to the shielding member, the conductive elastic member having a protrusion that protrudes outward from an opening provided in the housing and that electrically contacts the conductive member of the electronic device when the cartridge is inserted into the electronic device. 11. The cartridge for an electronic device according to claim 10, comprising a plurality of said conductive elastic members, at least one of said conductive elastic members being in electrical contact with a conductive member of said electronic device when said cartridge is inserted into said electronic device. 12. The electronic device cartridge according to claim 11, wherein the plurality of conductive elastic members electrically connect the shielding member to the power supply wiring of the circuit board. 13. The electronic device cartridge according to claim 7, further comprising: a metal heat dissipation member fixed to the metal housing element and positioned inside the housing facing the top surface of the second processor; and an interposition member interposed between the heat dissipation member and the top surface of the second processor and in close contact with the heat dissipation member and the second processor. 14. The electronic device cartridge according to claim 13, further comprising an elastic member for urging the second processor toward the heat dissipation member. 15. The electronic device cartridge of claim 3, wherein the substrate includes a connector for expansion memory. 16. The electronic device cartridge according to claim 15, wherein the housing has an expansion slot for inserting expansion memory into the expansion memory connector, and a removable expansion slot cover, the expansion slot cover being located in a position that is hidden within the electronic device when the cartridge is inserted into the electronic device. 17. The cartridge for an electronic device according to claim 16, wherein the expansion memory is configured as an IC card. 18. The electronic device cartridge according to claim 1, further comprising a connecting means for mechanically connecting the electronic device main body and the electronic device cartridge. 19. The electronic device cartridge according to claim 18, wherein the connecting means includes locking means and switch means for turning on power to the electronic device cartridge in response to the locking of the anchoring means. 20. An electronic device cartridge inserted through a predetermined insertion port into an electronic device having a first processor capable of logical operations, the electronic device cartridge comprising: a circuit board carrying electronic components for the cartridge; a housing having a through-hole for accommodating the circuit board; a conductive shielding member; and connecting means for electrically connecting the shielding member to the power supply wiring of the circuit board at at least one location between both ends of the through-hole in the housing. 21. An electronic device cartridge that is inserted through a predetermined insertion port into an electronic device having a first processor capable of logical operations, the electronic device cartridge comprising: a circuit board carrying electronic components within the cartridge; a housing that houses the circuit board and has a through-hole; and a conductive shielding member, the shielding member being provided in at least one location of the through-hole of the housing. 22. An electronic system comprising an electronic device and an electronic device cartridge inserted through a predetermined insertion slot of the electronic device, wherein the electronic device comprises a first processor capable of performing logical operations, and the electronic device cartridge comprises a conductive shielding member and a connecting means for electrically connecting the shielding member to a conductive member of the electronic device. 23. The electronic system of claim 22, wherein the electronic device cartridge further includes a second processor and a circuit board on which the second processor is mounted, and the connecting means includes means for electrically connecting the shielding member, power supply wiring on the circuit board, and conductive members of the electronic device. 24. The electronic system of claim 23, wherein the electronic device cartridge further comprises a housing that houses the substrate, the housing including the shielding member. 25. The electronic system of claim 24, wherein at least a portion of the housing is made of metal. 26. The electronic system of claim 24, wherein at least a portion of the housing has a conductive layer. 27. An electronic device cartridge that is inserted into an electronic device through a predetermined insertion port, the electronic device cartridge comprising: a circuit board with a digital processor mounted thereon; a housing that houses the circuit board; and grounding means that electrically connects the conductive portion of the electronic device, the power supply wiring of the circuit board, and the shielding member. 28. An electronic device cartridge inserted through a predetermined insertion port into an electronic device having a first processor capable of logical operations and a connector to which at least the address signal lines of the first processor are connected, the electronic device cartridge comprising: a second processor; data extraction means for extracting data reflected in an address signal output from the electronic device; a housing having a conductive shielding member and housing the second processor; and connection means for electrically connecting the conductive member of the electronic device, the power supply wiring of the board, and the shielding member. 29. An electronic device cartridge inserted through a predetermined insertion slot into an electronic device having a first processor capable of logical operations, first storage means storing the operations executed by the processor, a connector connected to at least an address signal line of the first processor, and address output means for reflecting data to be transferred externally in an address signal and outputting the address signal through the connector, the electronic device cartridge comprising: a second processor; second storage means storing the processing procedures executed by the second processor; data extraction means for extracting data reflected in the address from the address signal output from the electronic device; a circuit board mounting the second processor, second storage means, and data extraction means; a housing having a conductive shielding member and housing the circuit board; and grounding means electrically connecting the conductive portion of the electronic device, the power supply wiring of the circuit board, and the shielding member. 30. An electronic system comprising an electronic device cartridge according to any one of claims 1 to 21, 27, 28, and 29, and an electronic device.