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JPS6489558A - Dynamic random access memory - Google Patents

Dynamic random access memory

Info

Publication number
JPS6489558A
JPS6489558A JP62246968A JP24696887A JPS6489558A JP S6489558 A JPS6489558 A JP S6489558A JP 62246968 A JP62246968 A JP 62246968A JP 24696887 A JP24696887 A JP 24696887A JP S6489558 A JPS6489558 A JP S6489558A
Authority
JP
Japan
Prior art keywords
igfet
random access
access memory
fet
dynamic random
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62246968A
Other languages
Japanese (ja)
Inventor
Koji Otsu
Hiroyuki Yamada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP62246968A priority Critical patent/JPS6489558A/en
Publication of JPS6489558A publication Critical patent/JPS6489558A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/63—Vertical IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices

Landscapes

  • Dram (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)

Abstract

PURPOSE:To facilitate manufacture of a high-density memory by employing a cell arrangement in which a write IGFET and a read IGFET are vertically formed along the depth of grooves in a semiconductor substrate. CONSTITUTION:Isolation regions 13A and 13B are formed at the surface of a P<->-silicon substrate 10 by filling SiO2 in grooves 12A and 12B. These isolation regions define a region 14 for device formation between them, in which a memory cell 9 is formed. The memory cell includes a write IGFET (NMOS FET) 1, a data storage capacitor 4, and a PMOS FET 5 for readout. The NMOS FET 1 is formed vertically along a side wall 11A of a groove 11, while the PMOS FET 5 is formed vertically along a side wall 11B of the groove 11.
JP62246968A 1987-09-30 1987-09-30 Dynamic random access memory Pending JPS6489558A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62246968A JPS6489558A (en) 1987-09-30 1987-09-30 Dynamic random access memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62246968A JPS6489558A (en) 1987-09-30 1987-09-30 Dynamic random access memory

Publications (1)

Publication Number Publication Date
JPS6489558A true JPS6489558A (en) 1989-04-04

Family

ID=17156402

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62246968A Pending JPS6489558A (en) 1987-09-30 1987-09-30 Dynamic random access memory

Country Status (1)

Country Link
JP (1) JPS6489558A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0601590A3 (en) * 1992-12-10 1997-05-02 Sony Corp Semiconductor memory cell.

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0601590A3 (en) * 1992-12-10 1997-05-02 Sony Corp Semiconductor memory cell.
KR100286087B1 (en) * 1992-12-10 2001-04-16 이데이 노부유끼 Semiconductor memory cell

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