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JPS6488992A - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit

Info

Publication number
JPS6488992A
JPS6488992A JP62243732A JP24373287A JPS6488992A JP S6488992 A JPS6488992 A JP S6488992A JP 62243732 A JP62243732 A JP 62243732A JP 24373287 A JP24373287 A JP 24373287A JP S6488992 A JPS6488992 A JP S6488992A
Authority
JP
Japan
Prior art keywords
circuit
turned
capacity
level
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62243732A
Other languages
Japanese (ja)
Inventor
Yoshiki Kawajiri
Ryoichi Hori
Goro Kitsukawa
Takao Watabe
Takayuki Kawahara
Kiyoo Ito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP62243732A priority Critical patent/JPS6488992A/en
Publication of JPS6488992A publication Critical patent/JPS6488992A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To obtain a timing pulse having a stable phase time by charging and discharging capacity with constant current and delaying a signal in a delay circuit generating the other signal after a fixed time when it receives an inputted signal. CONSTITUTION:A semiconductor integrated circuit is constituted by a constant voltage circuit, a constant current circuit, switches SW1 and SW2, the capacity C and a level detection circuit. When it is operated, the input IN is set at a low level, the inverse input IN is set at a high level, the SW1 is turned on, the SW2 is turned off and constant voltage generated by the constant voltage circuit is charged to the capacity C. At such a time, the level detection circuit is not operated and the output OUT is the low level. Then, when the input IN is changed to the high level and the inverse input IN is changed to the low level, the SW1 is turned OFF and the SW2 is turned on. Besides, electric charge accumulated in the capacity C is discharged in a fixed current (i) through the SW2 by the constant current circuit, the voltage of a node 10 falls in a straight line and the output OUT is raised to the high level by the level detection circuit when the voltage is fixed.
JP62243732A 1987-09-30 1987-09-30 Semiconductor integrated circuit Pending JPS6488992A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62243732A JPS6488992A (en) 1987-09-30 1987-09-30 Semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62243732A JPS6488992A (en) 1987-09-30 1987-09-30 Semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPS6488992A true JPS6488992A (en) 1989-04-03

Family

ID=17108166

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62243732A Pending JPS6488992A (en) 1987-09-30 1987-09-30 Semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPS6488992A (en)

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