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JPS64813A - Noise eliminating circuit - Google Patents

Noise eliminating circuit

Info

Publication number
JPS64813A
JPS64813A JP62156093A JP15609387A JPS64813A JP S64813 A JPS64813 A JP S64813A JP 62156093 A JP62156093 A JP 62156093A JP 15609387 A JP15609387 A JP 15609387A JP S64813 A JPS64813 A JP S64813A
Authority
JP
Japan
Prior art keywords
circuit
signal
input
outputs
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62156093A
Other languages
Japanese (ja)
Other versions
JPH01813A (en
Inventor
Hiroshi Asada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP62156093A priority Critical patent/JPS64813A/en
Publication of JPH01813A publication Critical patent/JPH01813A/en
Publication of JPS64813A publication Critical patent/JPS64813A/en
Pending legal-status Critical Current

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  • Manipulation Of Pulses (AREA)

Abstract

PURPOSE: To easily make a circuit into a high density integrated circuit by providing a D-FF with a clear terminal and inputting an AND signal to the clock terminal and inputting a OR signal to the clear terminal.
CONSTITUTION: An input signal S10 has the waveform shaped by a Schmitt trigger circuit 1 and is inputted to a shift register 20 as a signal S12. The register 20 has a functional constitution to obtain four-stage shift outputs of the input signal and outputs signals S13∼S16. Signals S13∼S16 are processed in a four-input AND gate 30 by AND operation and are processed in a four-input OR gate 40 by OR operation. Processing outputs S18 and S17 are given to terminals CK and CLR of a D-FF circuit 5 with clear respectively, and the output where noise is eliminated is obtained from the output of the circuit 5. Thus, the circuit having the noise eliminating characteristic is constituted of a digital integrated circuit and the circuit is easily made into a high density integrated circuit.
COPYRIGHT: (C)1989,JPO&Japio
JP62156093A 1987-06-23 1987-06-23 Noise eliminating circuit Pending JPS64813A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62156093A JPS64813A (en) 1987-06-23 1987-06-23 Noise eliminating circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62156093A JPS64813A (en) 1987-06-23 1987-06-23 Noise eliminating circuit

Publications (2)

Publication Number Publication Date
JPH01813A JPH01813A (en) 1989-01-05
JPS64813A true JPS64813A (en) 1989-01-05

Family

ID=15620155

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62156093A Pending JPS64813A (en) 1987-06-23 1987-06-23 Noise eliminating circuit

Country Status (1)

Country Link
JP (1) JPS64813A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1990219A2 (en) 2007-05-10 2008-11-12 ATMEL Germany GmbH Wheel electronics and tyre monitoring system for measuring an indicator
JP2010206398A (en) * 2009-03-02 2010-09-16 Fujitsu Semiconductor Ltd Latch circuit, flip-flop circuit and semiconductor device
JP2010220674A (en) * 2009-03-19 2010-10-07 Toyomaru Industry Co Ltd Game machine

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52137964A (en) * 1976-05-14 1977-11-17 Omron Tateisi Electronics Co Preset counter

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52137964A (en) * 1976-05-14 1977-11-17 Omron Tateisi Electronics Co Preset counter

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1990219A2 (en) 2007-05-10 2008-11-12 ATMEL Germany GmbH Wheel electronics and tyre monitoring system for measuring an indicator
EP1990219A3 (en) * 2007-05-10 2009-09-09 Atmel Automotive GmbH Wheel electronics and tyre monitoring system for measuring an indicator
US7928838B2 (en) 2007-05-10 2011-04-19 Atmel Automotive Gmbh Wheel electronics and tire control system for measuring a measurand
JP2010206398A (en) * 2009-03-02 2010-09-16 Fujitsu Semiconductor Ltd Latch circuit, flip-flop circuit and semiconductor device
JP2010220674A (en) * 2009-03-19 2010-10-07 Toyomaru Industry Co Ltd Game machine

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