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JPS6478315A - Interval timer controller - Google Patents

Interval timer controller

Info

Publication number
JPS6478315A
JPS6478315A JP62235565A JP23556587A JPS6478315A JP S6478315 A JPS6478315 A JP S6478315A JP 62235565 A JP62235565 A JP 62235565A JP 23556587 A JP23556587 A JP 23556587A JP S6478315 A JPS6478315 A JP S6478315A
Authority
JP
Japan
Prior art keywords
counter
clock
synchronizing
constitution
interval timer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62235565A
Other languages
Japanese (ja)
Inventor
Osamu Moriyama
Hiroyuki Kishimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
PFU Ltd
Original Assignee
PFU Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by PFU Ltd filed Critical PFU Ltd
Priority to JP62235565A priority Critical patent/JPS6478315A/en
Publication of JPS6478315A publication Critical patent/JPS6478315A/en
Pending legal-status Critical Current

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  • Executing Machine-Instructions (AREA)

Abstract

PURPOSE:To shorten the access time of a timer counter with a simple constitution by securing such a constitution where the timer counter works synchronously with a data processor by the counter clock received from a synchronizing circuit. CONSTITUTION:A synchronizing circuit 7 synchronized a basic clock CLK2 for a timer counter from an oscillator 4 by a machine clock CLK1, and supplies this synchronizing output to the counter 3 as a counter clock. Thus the counter 3 counts the counter clocks in the timing of the CLK1 and therefore works synchronously with a data processor 1. As a result, no synchronizing time is required when the processor 1 reads and writes the counter 3. Then the access time of the counter 3 is shortened.
JP62235565A 1987-09-18 1987-09-18 Interval timer controller Pending JPS6478315A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62235565A JPS6478315A (en) 1987-09-18 1987-09-18 Interval timer controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62235565A JPS6478315A (en) 1987-09-18 1987-09-18 Interval timer controller

Publications (1)

Publication Number Publication Date
JPS6478315A true JPS6478315A (en) 1989-03-23

Family

ID=16987874

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62235565A Pending JPS6478315A (en) 1987-09-18 1987-09-18 Interval timer controller

Country Status (1)

Country Link
JP (1) JPS6478315A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004512614A (en) * 2000-10-27 2004-04-22 サンマイクロシステムズ　インコーポレーテッド Hardware architecture of a multi-mode power management system using a fixed time reference for operating system support

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5111906A (en) * 1974-07-18 1976-01-30 Tokyo Kaken Kk ICHINENSEISHOKUBUTSUKARA SENISOOSAISHUSURUHOHO OYOBI SOCHI

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5111906A (en) * 1974-07-18 1976-01-30 Tokyo Kaken Kk ICHINENSEISHOKUBUTSUKARA SENISOOSAISHUSURUHOHO OYOBI SOCHI

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004512614A (en) * 2000-10-27 2004-04-22 サンマイクロシステムズ　インコーポレーテッド Hardware architecture of a multi-mode power management system using a fixed time reference for operating system support

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