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JPS647714A - Clock synchronizing circuit - Google Patents

Clock synchronizing circuit

Info

Publication number
JPS647714A
JPS647714A JP62161264A JP16126487A JPS647714A JP S647714 A JPS647714 A JP S647714A JP 62161264 A JP62161264 A JP 62161264A JP 16126487 A JP16126487 A JP 16126487A JP S647714 A JPS647714 A JP S647714A
Authority
JP
Japan
Prior art keywords
circuit
clock component
constant voltage
pull
clock
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62161264A
Other languages
Japanese (ja)
Inventor
Yutaka Koizumi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62161264A priority Critical patent/JPS647714A/en
Publication of JPS647714A publication Critical patent/JPS647714A/en
Pending legal-status Critical Current

Links

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)

Abstract

PURPOSE:To attain the pull-in of a short time by detecting the presence or absence of the output of a full-wave rectifying circuit and selecting a constant voltage signal through a switching circuit when an output is not executed, in the clock synchronizing circuit of an N value PSK and QAM modulating system receiving side demodulator. CONSTITUTION:The clock component of respective base band signals P and Q of an N value PSK and QAM modulating wave is fetched by a full-wave rectifying circuit 1, processed by a loop circuit formed by a phase comparator 4, a switching circuit 8, an LPF5, a VCO 6, etc., through a synthesizing circuit 2 and a BPF3 and phase-locked-controlled. When the level of a clock component through the circuit 2 is detected and a clock component is absent, the circuit 8 is switched, a constant voltage from a constant voltage generating circuit 9 is supplied to a loop, and even when the clock component is absent, the pull out quantity does not become larger. As a result, the pull-in can always be executed in a short time.
JP62161264A 1987-06-30 1987-06-30 Clock synchronizing circuit Pending JPS647714A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62161264A JPS647714A (en) 1987-06-30 1987-06-30 Clock synchronizing circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62161264A JPS647714A (en) 1987-06-30 1987-06-30 Clock synchronizing circuit

Publications (1)

Publication Number Publication Date
JPS647714A true JPS647714A (en) 1989-01-11

Family

ID=15731796

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62161264A Pending JPS647714A (en) 1987-06-30 1987-06-30 Clock synchronizing circuit

Country Status (1)

Country Link
JP (1) JPS647714A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06197014A (en) * 1992-12-25 1994-07-15 Mitsubishi Electric Corp Phase locked loop circuit
JP2009189043A (en) * 2009-04-13 2009-08-20 Thomson Licensing OFDM signal sample phase detection

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06197014A (en) * 1992-12-25 1994-07-15 Mitsubishi Electric Corp Phase locked loop circuit
JP2009189043A (en) * 2009-04-13 2009-08-20 Thomson Licensing OFDM signal sample phase detection

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