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JPS647695A - Manufacture of multi-layer printed wiring board - Google Patents

Manufacture of multi-layer printed wiring board

Info

Publication number
JPS647695A
JPS647695A JP16312487A JP16312487A JPS647695A JP S647695 A JPS647695 A JP S647695A JP 16312487 A JP16312487 A JP 16312487A JP 16312487 A JP16312487 A JP 16312487A JP S647695 A JPS647695 A JP S647695A
Authority
JP
Japan
Prior art keywords
prepreg
etching resist
copper foil
insulating substrate
deposited
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16312487A
Other languages
Japanese (ja)
Inventor
Megumi Aoyanagi
Yoshiaki Sonoda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP16312487A priority Critical patent/JPS647695A/en
Publication of JPS647695A publication Critical patent/JPS647695A/en
Pending legal-status Critical Current

Links

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

PURPOSE:To manufacture a highly reliable multi-layer printed wiring board securely integrated without requiring any complicated process by laminating powdered glass-containing epoxy resin as an etching resist and a prepreg and pressing them without removing the resist. CONSTITUTION:A pattern 3 of an etching resist made of powdered glass- containing epoxy resin is formed on a conductor layer 2 deposited on an insulating substrate 1, and the conductor layer 2 is etched to form a circuit pattern 2'. Then, a prepreg layer including as a resin component epoxy resin is laminated without removing the etching resist 3 on the insulating substrate 1, on which the circuit pattern 2' is formed, and pressed to form an insulator layer 4. For example, a copper foil 2 is further placed on the insulating substrate 1 upon laminating the prepreg 4, and pressed integrally. An etching resist is deposited on the deposited copper foil 2, followed by proper repetition of processes of the formation of a desired pattern by etching and of placing of a prepreg and a copper foil, etc.
JP16312487A 1987-06-30 1987-06-30 Manufacture of multi-layer printed wiring board Pending JPS647695A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16312487A JPS647695A (en) 1987-06-30 1987-06-30 Manufacture of multi-layer printed wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16312487A JPS647695A (en) 1987-06-30 1987-06-30 Manufacture of multi-layer printed wiring board

Publications (1)

Publication Number Publication Date
JPS647695A true JPS647695A (en) 1989-01-11

Family

ID=15767640

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16312487A Pending JPS647695A (en) 1987-06-30 1987-06-30 Manufacture of multi-layer printed wiring board

Country Status (1)

Country Link
JP (1) JPS647695A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0690084A (en) * 1992-05-15 1994-03-29 Morton Internatl Inc Manufacture of multilayer printed-circuit board and its product

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0690084A (en) * 1992-05-15 1994-03-29 Morton Internatl Inc Manufacture of multilayer printed-circuit board and its product

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