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JPS6473599A - Storage device - Google Patents

Storage device

Info

Publication number
JPS6473599A
JPS6473599A JP62230677A JP23067787A JPS6473599A JP S6473599 A JPS6473599 A JP S6473599A JP 62230677 A JP62230677 A JP 62230677A JP 23067787 A JP23067787 A JP 23067787A JP S6473599 A JPS6473599 A JP S6473599A
Authority
JP
Japan
Prior art keywords
preset
circuits
level
storage
storage circuits
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62230677A
Other languages
Japanese (ja)
Inventor
Takashi Nakatani
Hiroshi Kobayashi
Shinji Suda
Takeshi Shibazaki
Terukuni Kubo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP62230677A priority Critical patent/JPS6473599A/en
Publication of JPS6473599A publication Critical patent/JPS6473599A/en
Pending legal-status Critical Current

Links

Landscapes

  • Static Random-Access Memory (AREA)
  • Dram (AREA)

Abstract

PURPOSE:To surely preset a storage element by providing a preset signal delay means to input a preset signal by adding time difference at every group that plural storage circuits are divided into some groups. CONSTITUTION:When a preset signal is inputted to a preset line 12a, OR circuits 10a and 10b are activated, word lines 9a and 9b go to an H level and storage circuits 8a and 8b go in a conducting condition with a bit line 6. On the other hand, the preset signal makes a third transistor 15 into the conducting condition, makes the bit line to an L level, the L is written into the storage elements 8a and 8b, the signal is delayed a little by a delay circuit 18 and comes out to a preset line 12b. This delayed preset signal makes OR circuits 10c-10e operate and makes word lines 9c-9e to the H level. At this time, by a third transistor 15 and the storage circuits 8a and 8b into which the L is already written, the data of the bit line 6 is made to the L level and since the L is surely written into storage circuits 8c-8e, the storage circuits 8c-8e are surely preset.
JP62230677A 1987-09-14 1987-09-14 Storage device Pending JPS6473599A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62230677A JPS6473599A (en) 1987-09-14 1987-09-14 Storage device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62230677A JPS6473599A (en) 1987-09-14 1987-09-14 Storage device

Publications (1)

Publication Number Publication Date
JPS6473599A true JPS6473599A (en) 1989-03-17

Family

ID=16911574

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62230677A Pending JPS6473599A (en) 1987-09-14 1987-09-14 Storage device

Country Status (1)

Country Link
JP (1) JPS6473599A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01213890A (en) * 1988-02-20 1989-08-28 Sony Corp Memory device
JPH02263384A (en) * 1989-04-03 1990-10-26 Mitsubishi Electric Corp Storage device
JPH02263383A (en) * 1989-04-03 1990-10-26 Mitsubishi Electric Corp Data erasing method for storage device
JPH04111293A (en) * 1990-08-30 1992-04-13 Nec Ic Microcomput Syst Ltd Semiconductor memory
JPH04298890A (en) * 1991-03-26 1992-10-22 Nec Ic Microcomput Syst Ltd Random access memory device
JP2006202397A (en) * 2005-01-20 2006-08-03 Fujitsu Ltd Semiconductor memory

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01213890A (en) * 1988-02-20 1989-08-28 Sony Corp Memory device
JPH02263384A (en) * 1989-04-03 1990-10-26 Mitsubishi Electric Corp Storage device
JPH02263383A (en) * 1989-04-03 1990-10-26 Mitsubishi Electric Corp Data erasing method for storage device
JPH04111293A (en) * 1990-08-30 1992-04-13 Nec Ic Microcomput Syst Ltd Semiconductor memory
JPH04298890A (en) * 1991-03-26 1992-10-22 Nec Ic Microcomput Syst Ltd Random access memory device
JP2006202397A (en) * 2005-01-20 2006-08-03 Fujitsu Ltd Semiconductor memory

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