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JPS6471348A - Signal processing circuit - Google Patents

Signal processing circuit

Info

Publication number
JPS6471348A
JPS6471348A JP62229024A JP22902487A JPS6471348A JP S6471348 A JPS6471348 A JP S6471348A JP 62229024 A JP62229024 A JP 62229024A JP 22902487 A JP22902487 A JP 22902487A JP S6471348 A JPS6471348 A JP S6471348A
Authority
JP
Japan
Prior art keywords
signal
transmission
control signals
multiplex
application
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62229024A
Other languages
Japanese (ja)
Inventor
Nobuo Sugino
Yoshikazu Suehiro
Kazuo Matsumura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP62229024A priority Critical patent/JPS6471348A/en
Publication of JPS6471348A publication Critical patent/JPS6471348A/en
Pending legal-status Critical Current

Links

Landscapes

  • Time-Division Multiplex Systems (AREA)
  • Communication Control (AREA)

Abstract

PURPOSE:To attain synchronizing signal transmission and asynchronizing signal transmission simultaneously by adding one application signal to a data signal, a clock signal and two control signals and sending them multiplexedly. CONSTITUTION:In receiving a data signal (a), a clock signal (b) and control signals (c), (d) requiring synchronizing transmission, they are converted into a TTL level by a level conversion circuit 1. The converted data signal a', clock signal b', control signals c', d' are fed to a signal multiplex transmission circuit 2. Moreover, the signal subjected to asynchronous transmission is fed to a signal multiplex transmission circuit 2 as the application signal (e). Then the transmission circuit 2 applies time division multiplex to the data signal a', the clock signal b', the control signals c', d' and the application signal (e) to convert the parallel signal into a serial signal and supplies the multiplex signal (f) to the transmission line 3.
JP62229024A 1987-09-11 1987-09-11 Signal processing circuit Pending JPS6471348A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62229024A JPS6471348A (en) 1987-09-11 1987-09-11 Signal processing circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62229024A JPS6471348A (en) 1987-09-11 1987-09-11 Signal processing circuit

Publications (1)

Publication Number Publication Date
JPS6471348A true JPS6471348A (en) 1989-03-16

Family

ID=16885554

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62229024A Pending JPS6471348A (en) 1987-09-11 1987-09-11 Signal processing circuit

Country Status (1)

Country Link
JP (1) JPS6471348A (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4863603A (en) * 1971-12-06 1973-09-04
JPS60112332A (en) * 1983-11-22 1985-06-18 Mitsubishi Electric Corp Digital multiplexing device
JPS6259433A (en) * 1985-09-05 1987-03-16 ノーザン・テレコム・リミテッド Digital transmission system

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4863603A (en) * 1971-12-06 1973-09-04
JPS60112332A (en) * 1983-11-22 1985-06-18 Mitsubishi Electric Corp Digital multiplexing device
JPS6259433A (en) * 1985-09-05 1987-03-16 ノーザン・テレコム・リミテッド Digital transmission system

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