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JPS6469064A - Manufacture of oxide superconducting wiring - Google Patents

Manufacture of oxide superconducting wiring

Info

Publication number
JPS6469064A
JPS6469064A JP62227636A JP22763687A JPS6469064A JP S6469064 A JPS6469064 A JP S6469064A JP 62227636 A JP62227636 A JP 62227636A JP 22763687 A JP22763687 A JP 22763687A JP S6469064 A JPS6469064 A JP S6469064A
Authority
JP
Japan
Prior art keywords
oxide superconducting
diffusion layer
wiring
superconducting film
insulator
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62227636A
Other languages
Japanese (ja)
Inventor
Hisanao Tsuge
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62227636A priority Critical patent/JPS6469064A/en
Publication of JPS6469064A publication Critical patent/JPS6469064A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204Conductive materials
    • H01L23/53285Conductive materials containing superconducting materials
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00Superconducting devices
    • H10N60/01Manufacture or treatment
    • H10N60/0268Manufacture or treatment of devices comprising copper oxide
    • H10N60/0661Processes performed after copper oxide formation, e.g. patterning
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Superconductor Devices And Manufacturing Methods Thereof (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Superconductors And Manufacturing Methods Therefor (AREA)

Abstract

PURPOSE:To unnecessitate direct patterning for forming a wiring, and enable flattening the wiring, by turning selectively an oxide superconducting film on a diffusion layer into insulator by applying solid phase reaction between the diffusion layer and the oxide superconducting film. CONSTITUTION:On a substrate 11, a diffusion layer composed of silicon dioxide (SiO2) and the like is stuck, which is worked by lithography process using an inverting mask of a wiring and reactive ion etching, and a diffusion layer pat tern 12 is formed. Then on the whole surface of the substrate 11, an oxide superconducting film 13 having a composition approximate to stoichiometric composition YBa2Cu3O7 is stuck. The sample is subjected to heat treatment at 850-1000 deg.C in oxygen flow for about several hours, the oxide superconducting film 13 is crystallized, and simultaneously the oxide superconducting film on the diffusion layer pattern 12 is turned into insulator by mutual diffusion. There by, forming an oxide superconducting wiring 15 surrounded by a region 14 turned into insulator.
JP62227636A 1987-09-10 1987-09-10 Manufacture of oxide superconducting wiring Pending JPS6469064A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62227636A JPS6469064A (en) 1987-09-10 1987-09-10 Manufacture of oxide superconducting wiring

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62227636A JPS6469064A (en) 1987-09-10 1987-09-10 Manufacture of oxide superconducting wiring

Publications (1)

Publication Number Publication Date
JPS6469064A true JPS6469064A (en) 1989-03-15

Family

ID=16863995

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62227636A Pending JPS6469064A (en) 1987-09-10 1987-09-10 Manufacture of oxide superconducting wiring

Country Status (1)

Country Link
JP (1) JPS6469064A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0612114A2 (en) * 1993-02-15 1994-08-24 Sumitomo Electric Industries, Ltd. Method for forming a patterned oxide superconductor thin film
EP0671764A3 (en) * 1990-10-31 1995-10-11 Sumitomo Electric Industries

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60239074A (en) * 1984-05-14 1985-11-27 Fujitsu Ltd Manufacture of josephson integrated circuit
JPS63291485A (en) * 1987-05-25 1988-11-29 Fujikura Ltd Manufacture of oxide superconducting circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60239074A (en) * 1984-05-14 1985-11-27 Fujitsu Ltd Manufacture of josephson integrated circuit
JPS63291485A (en) * 1987-05-25 1988-11-29 Fujikura Ltd Manufacture of oxide superconducting circuit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0671764A3 (en) * 1990-10-31 1995-10-11 Sumitomo Electric Industries
EP0612114A2 (en) * 1993-02-15 1994-08-24 Sumitomo Electric Industries, Ltd. Method for forming a patterned oxide superconductor thin film
EP0612114A3 (en) * 1993-02-15 1995-11-29 Sumitomo Electric Industries Method for forming a patterned oxide superconductor thin film.

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