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JPS6467794A - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit

Info

Publication number
JPS6467794A
JPS6467794A JP22717987A JP22717987A JPS6467794A JP S6467794 A JPS6467794 A JP S6467794A JP 22717987 A JP22717987 A JP 22717987A JP 22717987 A JP22717987 A JP 22717987A JP S6467794 A JPS6467794 A JP S6467794A
Authority
JP
Japan
Prior art keywords
digit lines
definit
signal
read data
logical
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP22717987A
Other languages
Japanese (ja)
Other versions
JP2555372B2 (en
Inventor
Hiroyuki Yamakoshi
Hideyasu Asai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC IC Microcomputer Systems Co Ltd
Original Assignee
NEC IC Microcomputer Systems Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC IC Microcomputer Systems Co Ltd filed Critical NEC IC Microcomputer Systems Co Ltd
Priority to JP22717987A priority Critical patent/JP2555372B2/en
Publication of JPS6467794A publication Critical patent/JPS6467794A/en
Application granted granted Critical
Publication of JP2555372B2 publication Critical patent/JP2555372B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

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  • Dram (AREA)
  • Static Random-Access Memory (AREA)

Abstract

PURPOSE:To speedify operation by generating a definit signal from the logical levels of the first and the second digit lines that are to be read data, and neglecting a time lapse prior to the determination of the difference in logical level between the said digit lines. CONSTITUTION:A definit signal generation circuit 4 which generates a definit signal representing that data read from a memory 2 is determined when the first and the second digit lines D, D is connected and the digit lines D, D become in different logical levels, is provided. Since the definit signal is generated from the logical levels of the digit lines D, D that are made read data by amplifying, the deviation caused by the time lapse prior to the determination of the difference in logical level between the first and the second digit lines D, D can be neglected. As a result, a margin for the time from when read data comes valid to when the definit signal is generated can be made extremely small, hence the operation can be speedified.
JP22717987A 1987-09-09 1987-09-09 Semiconductor integrated circuit Expired - Lifetime JP2555372B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22717987A JP2555372B2 (en) 1987-09-09 1987-09-09 Semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22717987A JP2555372B2 (en) 1987-09-09 1987-09-09 Semiconductor integrated circuit

Publications (2)

Publication Number Publication Date
JPS6467794A true JPS6467794A (en) 1989-03-14
JP2555372B2 JP2555372B2 (en) 1996-11-20

Family

ID=16856726

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22717987A Expired - Lifetime JP2555372B2 (en) 1987-09-09 1987-09-09 Semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JP2555372B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04177696A (en) * 1990-11-13 1992-06-24 Nec Corp Semiconductor memory circuit
JP2008016163A (en) * 2006-07-10 2008-01-24 Univ Of Tokyo Memory device and memory read error detection method

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6061985A (en) * 1983-09-14 1985-04-09 Mitsubishi Electric Corp Semiconductor memory
JPS63292484A (en) * 1987-05-26 1988-11-29 Toshiba Corp Semiconductor memory

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6061985A (en) * 1983-09-14 1985-04-09 Mitsubishi Electric Corp Semiconductor memory
JPS63292484A (en) * 1987-05-26 1988-11-29 Toshiba Corp Semiconductor memory

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04177696A (en) * 1990-11-13 1992-06-24 Nec Corp Semiconductor memory circuit
JP2008016163A (en) * 2006-07-10 2008-01-24 Univ Of Tokyo Memory device and memory read error detection method

Also Published As

Publication number Publication date
JP2555372B2 (en) 1996-11-20

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