JPS646537B2 - - Google Patents
Info
- Publication number
- JPS646537B2 JPS646537B2 JP22717683A JP22717683A JPS646537B2 JP S646537 B2 JPS646537 B2 JP S646537B2 JP 22717683 A JP22717683 A JP 22717683A JP 22717683 A JP22717683 A JP 22717683A JP S646537 B2 JPS646537 B2 JP S646537B2
- Authority
- JP
- Japan
- Prior art keywords
- heat treatment
- wafer
- layer
- ion implantation
- gettering
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000005468 ion implantation Methods 0.000 claims description 20
- 238000005247 gettering Methods 0.000 claims description 18
- 238000010438 heat treatment Methods 0.000 claims description 17
- 230000000694 effects Effects 0.000 claims description 15
- 150000002500 ions Chemical class 0.000 claims description 12
- 239000004065 semiconductor Substances 0.000 claims description 12
- 238000002513 implantation Methods 0.000 claims description 11
- 238000004519 manufacturing process Methods 0.000 claims description 6
- 238000000034 method Methods 0.000 claims description 6
- 239000000758 substrate Substances 0.000 claims 3
- 239000002184 metal Substances 0.000 claims 1
- 235000012431 wafers Nutrition 0.000 description 23
- 230000015556 catabolic process Effects 0.000 description 14
- 239000013078 crystal Substances 0.000 description 10
- 230000007547 defect Effects 0.000 description 10
- 238000009792 diffusion process Methods 0.000 description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 229910052710 silicon Inorganic materials 0.000 description 8
- 239000010703 silicon Substances 0.000 description 8
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 4
- 229910001385 heavy metal Inorganic materials 0.000 description 4
- 229910052698 phosphorus Inorganic materials 0.000 description 4
- 239000011574 phosphorus Substances 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 229910052786 argon Inorganic materials 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- ILAHWRKJUDSMFH-UHFFFAOYSA-N boron tribromide Chemical compound BrB(Br)Br ILAHWRKJUDSMFH-UHFFFAOYSA-N 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 230000003993 interaction Effects 0.000 description 2
- XHXFXVLFKHQFAL-UHFFFAOYSA-N phosphoryl trichloride Chemical compound ClP(Cl)(Cl)=O XHXFXVLFKHQFAL-UHFFFAOYSA-N 0.000 description 2
- 238000001953 recrystallisation Methods 0.000 description 2
- 229910015845 BBr3 Inorganic materials 0.000 description 1
- 229910019213 POCl3 Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 230000001747 exhibiting effect Effects 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 238000001125 extrusion Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 239000000700 radioactive tracer Substances 0.000 description 1
- 238000005488 sandblasting Methods 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
- H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Bipolar Transistors (AREA)
Description
【発明の詳細な説明】
「技術分野」
本発明は、ゲツタリングによる半導体装置の耐
圧特性改善の方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION TECHNICAL FIELD The present invention relates to a method for improving breakdown voltage characteristics of a semiconductor device by gettering.
「従来技術」
Pn接合の近傍に重金属イオン等が存在すると、
その部分に電界が集中し、全体の接合がブレーク
ダウンする前に局部的にブレークダウンし、耐圧
が低下する原因となる。このため、半導体装置の
動作に余り影響を与えない部分、たとえば半導体
ウエハの裏面にサンドブラストやイオン注入によ
つて機械的歪を与え、この歪層に重金属イオン等
を固定させて耐圧特性を改善する方法、いわゆる
ゲツタリング技術が知られている。"Prior art" When heavy metal ions etc. are present near the Pn junction,
The electric field concentrates in that part, causing local breakdown before the breakdown of the entire junction, causing a drop in breakdown voltage. For this reason, mechanical strain is applied to parts that do not significantly affect the operation of semiconductor devices, such as the back surface of the semiconductor wafer, by sandblasting or ion implantation, and heavy metal ions, etc. are fixed in this strained layer to improve the breakdown voltage characteristics. A method, the so-called gettering technique, is known.
イオン注入によるゲツタリングの例をシリコン
トランジスタの場合について説明する。まず、ｎ
形シリコンウエハの表面にボロンを拡散してＰ形
ベース層を形成する。次に、ウエハの裏面にAr
（アルゴン）イオンを注入した後、ウエハの表面
にリンを拡散してn+形エミツタ層およびコレク
タ電極のオーミツクコンタクト用n+形拡散層を
形成する。Ar注入によつてウエハの裏面近傍は
アモルフアス化し、多くの結晶欠陥が生じる。こ
の結晶欠陥が、引き続いて行なわれるリン拡散の
熱処理によつてウエハの表面側に伝播し、重金属
イオン等を固定するゲツタリングの効果を発揮す
る。 An example of gettering by ion implantation will be explained in the case of a silicon transistor. First, n
A P-type base layer is formed by diffusing boron onto the surface of a P-type silicon wafer. Next, Ar is applied to the backside of the wafer.
After implanting (argon) ions, phosphorus is diffused into the surface of the wafer to form an n + type emitter layer and an n + type diffusion layer for ohmic contact of the collector electrode. Due to Ar implantation, the vicinity of the back surface of the wafer becomes amorphous, and many crystal defects are generated. These crystal defects propagate to the surface side of the wafer through the subsequent heat treatment for phosphorus diffusion, producing a gettering effect that fixes heavy metal ions and the like.
このように、従来のイオン注入によるゲツタリ
ングは、イオン注入後の熱処理を比較的高温で行
なう必要があるとされていたため、この熱処理を
不純物拡散の際の900〜1200℃程度の熱処理に便
乗して行なつていた。 In this way, conventional gettering by ion implantation requires heat treatment after ion implantation to be performed at a relatively high temperature. I was doing it.
一方、本願の発明者等が上記従来のゲツタリン
グについて実験したところ、シリコンウエハの裏
面にArイオンを注入して1100℃程度の熱処理を
施したものでは、イオン注入による結晶欠陥がウ
エハの表面側にまで伝播して、拡散による歪や表
面から侵入した汚れ等との相互作用によつて、耐
圧低下の原因となる新たな結晶欠陥が形成される
場合のあることがわかつた。このため、従来のゲ
ツタリングでは、耐圧を向上させる効果と同時
に、その効果を打ち消す作用も含んでいることが
推測された。 On the other hand, when the inventors of this application conducted experiments on the conventional gettering described above, they found that when Ar ions were implanted into the back side of a silicon wafer and heat treatment was performed at approximately 1100°C, crystal defects due to the ion implantation were transferred to the front side of the wafer. It was found that new crystal defects, which cause a decrease in breakdown voltage, may be formed due to strain caused by diffusion and interaction with dirt that has entered from the surface. For this reason, it has been speculated that conventional gettering has the effect of improving breakdown voltage as well as the effect of canceling that effect.
「発明の目的」
本発明の目的は、イオン注入によるゲツタリン
グの効果を向上させ、半導体装置の耐圧特性を改
善することにある。[Object of the Invention] An object of the present invention is to improve the gettering effect by ion implantation and to improve the breakdown voltage characteristics of a semiconductor device.
「実施例」
第１図は、本発明を適用したシリコントランジ
スタの製造方法を示すものである。Embodiment FIG. 1 shows a method for manufacturing a silicon transistor to which the present invention is applied.
まず、ｎ形シリコンウエハ１の表面から、
SiO2膜２をマスクとしてボロンの選択拡散を行
ない、深さ2μのＰ形ベース層３を形成した（第
１図Ａ参照）。拡散温度は、BBr3を不純物源とプ
レデボジシヨンが950℃、ドライブインが1150℃
である。 First, from the surface of the n-type silicon wafer 1,
Using the SiO 2 film 2 as a mask, boron was selectively diffused to form a P-type base layer 3 with a depth of 2 μm (see FIG. 1A). Diffusion temperature is 950℃ for pre-deposition and 1150℃ for drive-in with BBr3 as impurity source.
It is.
次に、ベース層表面およびベース層と離れたウ
エハ１の表面にリンの選択拡散を行ない、深さ
1.5μのn+形エミツタ層４およびコレクタ電極のオ
ーミツクコンタクト用n+形拡散層５を形成した
（第１図Ｂ参照）。拡散温度は、POCl3を不純物源
とするプレデポジシヨンが950℃、ドライブイン
が1000℃である。このとき、エミツタ押出し効果
によつて、ベース幅は1μとなつた。なお、この
工程で600℃以上の熱処理工程は終了した。 Next, selective diffusion of phosphorus is performed on the surface of the base layer and the surface of the wafer 1 away from the base layer, and the depth
A 1.5 μm n + type emitter layer 4 and an n + type diffusion layer 5 for ohmic contact of the collector electrode were formed (see FIG. 1B). The diffusion temperature is 950°C for pre-deposition using POCl3 as an impurity source and 1000°C for drive-in. At this time, the base width was 1μ due to the emitter extrusion effect. Note that the heat treatment step at 600° C. or higher was completed in this step.
続いてウエハ１の裏面全面に、Arイオンの臨
界注入量（約3.5×1014個／cm2）を越える１×1016
個／cm2のAr注入を行ない、ウエハ１の裏面近傍
にアモルフアス化したイオン注入層６を形成した
（第１図Ｃ参照）。 Next, the entire back surface of wafer 1 is implanted with 1×10 16 Ar ions exceeding the critical implantation dose (approximately 3.5×10 14 ions/cm 2 ).
An amorphous ion-implanted layer 6 was formed in the vicinity of the back surface of the wafer 1 by performing Ar implantation at a rate of 1/cm 2 (see FIG. 1C).
次に、SiO2膜２を開孔し、Alを電子ビーム蒸
着し、このAlをパターン形成した後、N2雰囲気
中で480℃30分の熱処理を行ない、エミツタ電極
７、ベース電極８およびコレクタ電極９を形成し
た（第１図Ｄ参照）。この電極形成時の熱処理は、
イオン注入層６にゲツタリング効果を発揮させる
ための熱処理を兼ねたものである。 Next, holes are opened in the SiO 2 film 2, Al is deposited by electron beam, and after patterning of this Al, heat treatment is performed at 480°C for 30 minutes in an N 2 atmosphere to form the emitter electrode 7, base electrode 8, and collector electrode. An electrode 9 was formed (see FIG. 1D). The heat treatment during electrode formation is
This also serves as a heat treatment for causing the ion implantation layer 6 to exhibit a gettering effect.
なお、この実施例においては、ゲツタリングの
効果を明らかにするため、ベース幅1μに対し、
ベース面積が18.36mm2、エミツタ面積17.66mm2とい
う大面積のトランジスタを形成した。このため、
良品率はかなり低い値となつている。ウエハの厚
さは280μであつた。 In addition, in this example, in order to clarify the effect of gettering, for a base width of 1μ,
A transistor with a large base area of 18.36 mm 2 and emitter area of 17.66 mm 2 was formed. For this reason,
The rate of non-defective products is quite low. The thickness of the wafer was 280μ.
「発明の効果」
第２図は、第１図Ｄに示した本発明に係るトラ
ンジスタと従来のトランジスタについて、コレク
タ・ベース接合のブレークダウン電圧BVCBOを比
較したデータである。従来のトランジスタとは、
第１図の製造工程におけるAr注入工程をエミツ
タ拡散直前に繰り上げたもので、それ以外は本発
明に係るトランジスタの製造工程と全く同じ工程
で作られたものである。"Effects of the Invention" FIG. 2 shows data comparing the collector-base junction breakdown voltage BV CBO of the transistor according to the present invention shown in FIG. 1D and a conventional transistor. What is a conventional transistor?
The Ar implantation step in the manufacturing process shown in FIG. 1 is carried out immediately before the emitter diffusion, and the other steps are completely the same as the manufacturing process of the transistor according to the present invention.
第２図の耐圧のヒストグラムによれば、本発明
に係るトランジスタは、従来のトランジスタと比
べてBVCBOが全体的に高いことがわかる。また、
BVCBOが100V以上の試料数は、従来のトランジ
スタでは63個中21個（33.3％）であるのに対し
て、本発明に係るトランジスタでは63個中27個
（42.9％）であり、耐圧歩留りの向上が認められ
る。さらに、電流―電圧特性をカーブトレーサー
で観察すると、本発明に係るトランジスタでは、
鋭いブレークダウン特性（ハードブレークダウ
ン）を呈した試料数が従来のトランジスタの場合
より多かつた。 According to the withstand voltage histogram in FIG. 2, it can be seen that the transistor according to the present invention has a higher BV CBO overall than the conventional transistor. Also,
The number of samples with BV CBO of 100 V or more was 21 out of 63 (33.3%) for conventional transistors, while it was 27 out of 63 (42.9%) for transistors according to the present invention, indicating that the breakdown voltage yield was improvement was observed. Furthermore, when observing the current-voltage characteristics with a curve tracer, it was found that in the transistor according to the present invention,
The number of samples exhibiting sharp breakdown characteristics (hard breakdown) was greater than that of conventional transistors.
このように耐圧特性が改良される理由は、イオ
ン注入の後で行なう熱処理の温度が従来より大幅
に低いため、イオン注入により誘起された結晶欠
陥のウエハ表面側への伝播が少なく、従来例の項
で述べた相互作用による新たな結晶欠陥が発生し
ないためであると考えられる。また、イオン注入
量を臨界注入量以上とすることにより、比較的低
温の熱処理であつても、十分にゲツタリング効果
が発揮されるためであると考えられる。 The reason why the breakdown voltage characteristics are improved in this way is that the temperature of the heat treatment performed after ion implantation is much lower than in the past, so the propagation of crystal defects induced by ion implantation to the wafer surface side is reduced, and compared to the conventional example. This is thought to be because new crystal defects are not generated due to the interaction described in section 2. It is also believed that this is because by setting the ion implantation amount to a critical implantation amount or more, the gettering effect can be sufficiently exerted even when heat treatment is performed at a relatively low temperature.
なお、本発明においては、熱処理温度が低いた
め、アモルフアス化したイオン注入層が十分に再
結晶化しない恐れがある。しかし、アモルフアス
化する領域は半導体装置の動作に余り影響を与え
ない部分であること、および従来より低い温度と
は言つてもある程度の再結晶化は起こると考えら
れるので、実用上問題は起こらない。 In the present invention, since the heat treatment temperature is low, there is a possibility that the amorphous ion-implanted layer may not be sufficiently recrystallized. However, since the region that becomes amorphous does not have much effect on the operation of the semiconductor device, and it is thought that some recrystallization will occur even though the temperature is lower than before, there will be no practical problems. .
「その他」
ゲツタリングのためのイオン注入する元素とし
ては、シリコンウエハに対してはアルゴン、酸素
およびリンが効果的である。しかし、その他の元
素でも利用できないことはない。"Others" Argon, oxygen, and phosphorus are effective elements for ion implantation into silicon wafers for gettering. However, it is not impossible to use other elements as well.
イオン注入量については、前述のように、ゲツ
タリング効果の確実さを期すため、臨界注入量以
上とする。臨界注入量は、第３図に示すように、
イオン注入によつてイオン注入層を発生する結晶
欠陥密度が飽和する注入量であり、イオン注入し
た部分が全面的にアモルフアス化するときの注入
量に相当する。なお、臨界注入量を越えたときに
結晶欠陥密度が少し低下するのは、アモルフアス
化された層の再結晶化がイオン注入による結晶欠
陥の発生より支配的になるためと考えられる。 As described above, the ion implantation amount is set to be equal to or higher than the critical implantation amount in order to ensure the gettering effect. The critical injection amount is as shown in Figure 3.
This is the implantation amount at which the density of crystal defects generated in the ion-implanted layer is saturated by ion implantation, and corresponds to the implantation amount at which the ion-implanted portion becomes entirely amorphous. The reason why the crystal defect density slightly decreases when the critical implantation dose is exceeded is considered to be that recrystallization of the amorphous layer becomes more dominant than the generation of crystal defects due to ion implantation.
イオン注入後の熱処理温度としては、実用的に
は300〜60℃が適している。すなわち、600℃を越
えると、結晶欠陥が耐圧特性に与えるマイナスの
効果が大きくなる。300℃未満では、重金属イオ
ン等の移動が十分に起こらないので、ゲツタリン
グ効果が小さい。熱処理時間は重要なフアクタで
はないが、あまり短いとゲツタリングが十分に起
こらないので、少なくとも15分間以上、通常は30
分間程度もしくはそれ以上とする。 Practically speaking, a temperature of 300 to 60°C is suitable for the heat treatment temperature after ion implantation. That is, when the temperature exceeds 600°C, the negative effect that crystal defects have on the breakdown voltage characteristics increases. If the temperature is less than 300°C, the movement of heavy metal ions etc. does not occur sufficiently, so the gettering effect is small. The heat treatment time is not an important factor, but if it is too short, gettering will not occur sufficiently, so the heat treatment time is at least 15 minutes, usually 30 minutes.
It should be about a minute or more.
イオン注入する領域は、実施例のように、実質
的には半導体ウエハの表面近傍に半導体装置が作
り込まれている場合は、ウエハの裏面側領域にゲ
ツタリングのためのイオン注入を行なうのがよ
い。もちろん、ウエハ裏面の全面にイオン注入し
なければならないと言うものではなく、ウエハ裏
面のうちPn接合との対向領域に限つてイオン注
入するような方法を採ることもできる。また、エ
ピタキシヤル二重拡散形トランジスタや三重拡散
形トランジスタのような場合、ウエハ表面側にエ
ミツタ層とベース層が形成されており、ウエハ裏
面側は厚いコレクタ高抵抗層である。しかし、こ
のコレクタ高抵抗層はトランジスタ動作にはほと
んど関係しないので、ウエハ裏面のコレクタ高抵
抗層にゲツタリングのためのイオン注入層を形成
してもさしつかえない。 As for the region to be implanted with ions, when semiconductor devices are fabricated substantially near the surface of the semiconductor wafer, as in the example, it is preferable to perform ion implantation for gettering in the region on the back surface of the wafer. . Of course, it is not necessary to implant ions into the entire back surface of the wafer, but it is also possible to adopt a method in which ions are implanted only in the region of the back surface of the wafer that faces the Pn junction. Further, in the case of an epitaxial double diffusion type transistor or a triple diffusion type transistor, an emitter layer and a base layer are formed on the front side of the wafer, and a thick collector high resistance layer is formed on the back side of the wafer. However, since this collector high resistance layer has little to do with transistor operation, an ion implantation layer for gettering may be formed in the collector high resistance layer on the back surface of the wafer.
第１図は本発明の１実施例であるシリコントラ
ンジスタの製造方法を示す断面図、第２図は本発
明の１実施例および従来例のBVCBOに関するヒス
トグラム、第３図はイオン注入における臨界注入
量を説明するグラフである。
１……ｎ形シリコンウエハ、３……Ｐ形ベース
層、４……n+形エミツタ層、６……イオン注入
層、７……エミツタ電極。
Fig. 1 is a cross-sectional view showing a method of manufacturing a silicon transistor according to an embodiment of the present invention, Fig. 2 is a histogram regarding BV CBO of an embodiment of the present invention and a conventional example, and Fig. 3 is a critical implantation in ion implantation. It is a graph explaining the amount. DESCRIPTION OF SYMBOLS 1...N-type silicon wafer, 3...P-type base layer, 4...n + type emitter layer, 6...Ion implantation layer, 7...Emitter electrode.
Claims (1)
キー接合が一方の主面側に偏寄して形成されてい
る半導体基板に対して、600℃を越える熱処理を
すべて終了した後に、前記半導体基板の前記一方
の主面とは反対の主面から前記半導体基板中に臨
界注入量以上のイオンを注入してイオン注入層を
形成し、しかる後に300〜600℃の熱処理を施し、
前記イオン注入層に基づくゲツタリング作用によ
つて前記Pn接合もしくはシヨツトキー接合の耐
圧特性を改善することを特徴とする半導体装置の
製造方法。 ２ 前記600℃以下の熱処理が電極金属の熱処理
を兼ねて行なわれる特許請求の範囲第１項記載の
半導体装置の製造方法。[Claims] 1. After completing all heat treatment at a temperature exceeding 600° C. on a semiconductor substrate in which at least one Pn junction or Schottky junction is formed biased toward one main surface side, the semiconductor substrate forming an ion-implanted layer by implanting ions in an amount equal to or greater than a critical implantation amount into the semiconductor substrate from the main surface opposite to the one main surface, and then performing heat treatment at 300 to 600°C;
A method for manufacturing a semiconductor device, characterized in that the withstand voltage characteristics of the Pn junction or Schottky junction are improved by a gettering effect based on the ion implantation layer. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the heat treatment at 600° C. or lower also serves as heat treatment of the electrode metal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22717683A JPS60117738A (en) | 1983-11-30 | 1983-11-30 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22717683A JPS60117738A (en) | 1983-11-30 | 1983-11-30 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60117738A JPS60117738A (en) | 1985-06-25 |
| JPS646537B2 true JPS646537B2 (en) | 1989-02-03 |
Family
ID=16856672
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP22717683A Granted JPS60117738A (en) | 1983-11-30 | 1983-11-30 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60117738A (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5236872A (en) * | 1991-03-21 | 1993-08-17 | U.S. Philips Corp. | Method of manufacturing a semiconductor device having a semiconductor body with a buried silicide layer |
| US5757063A (en) * | 1994-03-25 | 1998-05-26 | Kabushiki Kaisha Toshiba | Semiconductor device having an extrinsic gettering film |
| JP3524141B2 (en) * | 1994-03-25 | 2004-05-10 | 株式会社東芝 | Semiconductor device and manufacturing method thereof |
| JP2011253983A (en) * | 2010-06-03 | 2011-12-15 | Disco Abrasive Syst Ltd | Method for adding gettering layer to silicon wafer |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5396666A (en) * | 1977-02-04 | 1978-08-24 | Hitachi Ltd | Manufacture of semiconductor device with pn junction |
| JPS5666046A (en) * | 1979-11-01 | 1981-06-04 | Sony Corp | Processing method of semiconductor substrate |
-
1983
- 1983-11-30 JP JP22717683A patent/JPS60117738A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS60117738A (en) | 1985-06-25 |
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