JPS6462773A - Wiring system for printed board - Google Patents
Wiring system for printed boardInfo
- Publication number
- JPS6462773A JPS6462773A JP62220764A JP22076487A JPS6462773A JP S6462773 A JPS6462773 A JP S6462773A JP 62220764 A JP62220764 A JP 62220764A JP 22076487 A JP22076487 A JP 22076487A JP S6462773 A JPS6462773 A JP S6462773A
- Authority
- JP
- Japan
- Prior art keywords
- area
- intersection
- train
- intersections
- land
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
PURPOSE:To eliminate the generation of a useless beer, and to contrive to shorten the wiring length, by checking an intersection state of a polygonal area and deriving an intersection area and the number of intersections, and using an intersection area train in which the sum of the number of intersection becomes the smallest as an area path for connecting two points. CONSTITUTION:In the shortest rectangular area A, an intersection area train for containing a wiring possible path extending from a land LA1 to a land LA2 therein, and the sum of the number of intersections in the intersection area train are derived. The intersection area train in which the sum of the number of intersections is the smallest is the intersection area train of A-1 A-6 A-7, and a wiring pattern for connecting the sections of the land LA1 and the land LA2 becomes such a shape as exists in an area A'. In this regard, when plural pieces of intersection area trains in which the sum of the number of intersections is the smallest exist, that of the smallest area among them is selected. In such a way, while evaluating the relative area intersection in the whole printed board or the divided block area, a path inference and a path determination can be executed, and a beer can be optimized.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62220764A JP2566788B2 (en) | 1987-09-03 | 1987-09-03 | Printed circuit board wiring method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62220764A JP2566788B2 (en) | 1987-09-03 | 1987-09-03 | Printed circuit board wiring method |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6462773A true JPS6462773A (en) | 1989-03-09 |
JP2566788B2 JP2566788B2 (en) | 1996-12-25 |
Family
ID=16756183
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62220764A Expired - Lifetime JP2566788B2 (en) | 1987-09-03 | 1987-09-03 | Printed circuit board wiring method |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2566788B2 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH08101854A (en) * | 1994-09-30 | 1996-04-16 | Nec Corp | Method for wiring design of integrated circuit |
JP2008242834A (en) * | 2007-03-27 | 2008-10-09 | O Shukuchin | Wiring position determination method for substrate, and substrate manufactured using this method |
-
1987
- 1987-09-03 JP JP62220764A patent/JP2566788B2/en not_active Expired - Lifetime
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH08101854A (en) * | 1994-09-30 | 1996-04-16 | Nec Corp | Method for wiring design of integrated circuit |
JP2008242834A (en) * | 2007-03-27 | 2008-10-09 | O Shukuchin | Wiring position determination method for substrate, and substrate manufactured using this method |
Also Published As
Publication number | Publication date |
---|---|
JP2566788B2 (en) | 1996-12-25 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
ES8506925A1 (en) | Memory identification apparatus. | |
DE69030528D1 (en) | Method and arrangement for testing circuit boards | |
DE69006772D1 (en) | Process for the steam reforming of hydrocarbons. | |
DE3483874D1 (en) | ARRANGEMENT FOR COHERENT SUBSIDAL REPRESENTATION IN RADAR EQUIPMENT. | |
DE3855860D1 (en) | Circuit change system and method, method for generating inverted logic and logic design system | |
FR2607773B1 (en) | SEMI-SUBMERSIBLE CATAMARAN-TYPE PLATFORM FOR DRILLING AT SEA | |
GB2168184B (en) | Minimum passage time navigation system for sailing vessels | |
DE3481398D1 (en) | METHOD AND CIRCUIT ARRANGEMENT FOR COMPENSATING CROSS-SPEED AND / OR ECHO SIGNALS. | |
DE3578206D1 (en) | DEVICE FOR GENERATING FLAMMABLE SOLID / GAS SUSPENSIONS. | |
JPS6462773A (en) | Wiring system for printed board | |
PH20683A (en) | Process for the flotation of base metal sulfide minerals in acid,neutral or middly alkaline circuits | |
DE68924304D1 (en) | Circuit for testing micro-controlled circuit blocks. | |
DE3585055D1 (en) | COMPUTER GRAPHICS METHOD FOR GENERATING A LEVEL GEOMETRIC PROJECTION. | |
JPS645100A (en) | Shortest route search system | |
JPS6462772A (en) | Terminal position determining system for function block in ic | |
TW333741B (en) | The pre-burn in DRAM module and module circuit board | |
JPS6413187A (en) | Display signal generation system | |
DE58909440D1 (en) | Method for securing secret code data stored in a data memory and circuit arrangement for carrying out the method. | |
JPS559971A (en) | Anti-vibration structure for ground | |
Kirby | Thaden, EC" Russia's Western Borderlands 1710-1870"(Book Review) | |
Michael et al. | Careless whisper | |
JPS5766700A (en) | Land and wiring pattern correcting system for printed board | |
DE69429380D1 (en) | Process for improving the statistical distribution in the copolymerization of olefins | |
JPS53145295A (en) | Method of cnstructing shipping | |
JPS52106246A (en) | Test method |