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JPS6462773A - Wiring system for printed board - Google Patents

Wiring system for printed board

Info

Publication number
JPS6462773A
JPS6462773A JP62220764A JP22076487A JPS6462773A JP S6462773 A JPS6462773 A JP S6462773A JP 62220764 A JP62220764 A JP 62220764A JP 22076487 A JP22076487 A JP 22076487A JP S6462773 A JPS6462773 A JP S6462773A
Authority
JP
Japan
Prior art keywords
area
intersection
train
intersections
land
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62220764A
Other languages
Japanese (ja)
Other versions
JP2566788B2 (en
Inventor
Seiichi Urita
Shozo Toda
Hisashi Urakuchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP62220764A priority Critical patent/JP2566788B2/en
Publication of JPS6462773A publication Critical patent/JPS6462773A/en
Application granted granted Critical
Publication of JP2566788B2 publication Critical patent/JP2566788B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Abstract

PURPOSE:To eliminate the generation of a useless beer, and to contrive to shorten the wiring length, by checking an intersection state of a polygonal area and deriving an intersection area and the number of intersections, and using an intersection area train in which the sum of the number of intersection becomes the smallest as an area path for connecting two points. CONSTITUTION:In the shortest rectangular area A, an intersection area train for containing a wiring possible path extending from a land LA1 to a land LA2 therein, and the sum of the number of intersections in the intersection area train are derived. The intersection area train in which the sum of the number of intersections is the smallest is the intersection area train of A-1 A-6 A-7, and a wiring pattern for connecting the sections of the land LA1 and the land LA2 becomes such a shape as exists in an area A'. In this regard, when plural pieces of intersection area trains in which the sum of the number of intersections is the smallest exist, that of the smallest area among them is selected. In such a way, while evaluating the relative area intersection in the whole printed board or the divided block area, a path inference and a path determination can be executed, and a beer can be optimized.
JP62220764A 1987-09-03 1987-09-03 Printed circuit board wiring method Expired - Lifetime JP2566788B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62220764A JP2566788B2 (en) 1987-09-03 1987-09-03 Printed circuit board wiring method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62220764A JP2566788B2 (en) 1987-09-03 1987-09-03 Printed circuit board wiring method

Publications (2)

Publication Number Publication Date
JPS6462773A true JPS6462773A (en) 1989-03-09
JP2566788B2 JP2566788B2 (en) 1996-12-25

Family

ID=16756183

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62220764A Expired - Lifetime JP2566788B2 (en) 1987-09-03 1987-09-03 Printed circuit board wiring method

Country Status (1)

Country Link
JP (1) JP2566788B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08101854A (en) * 1994-09-30 1996-04-16 Nec Corp Method for wiring design of integrated circuit
JP2008242834A (en) * 2007-03-27 2008-10-09 O Shukuchin Wiring position determination method for substrate, and substrate manufactured using this method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08101854A (en) * 1994-09-30 1996-04-16 Nec Corp Method for wiring design of integrated circuit
JP2008242834A (en) * 2007-03-27 2008-10-09 O Shukuchin Wiring position determination method for substrate, and substrate manufactured using this method

Also Published As

Publication number Publication date
JP2566788B2 (en) 1996-12-25

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