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JPS6461847A - Dma control circuit - Google Patents

Dma control circuit

Info

Publication number
JPS6461847A
JPS6461847A JP62218367A JP21836787A JPS6461847A JP S6461847 A JPS6461847 A JP S6461847A JP 62218367 A JP62218367 A JP 62218367A JP 21836787 A JP21836787 A JP 21836787A JP S6461847 A JPS6461847 A JP S6461847A
Authority
JP
Japan
Prior art keywords
address
dma
error
microprocessor
status signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62218367A
Other languages
Japanese (ja)
Inventor
Masazumi Nakatsugawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62218367A priority Critical patent/JPS6461847A/en
Publication of JPS6461847A publication Critical patent/JPS6461847A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Debugging And Monitoring (AREA)
  • Bus Control (AREA)

Abstract

PURPOSE:To realize the DMA transfer with high reliability, by inspecting the memory writing addresses in each transfer cycle during the DMA transfer so that the memory address which is possibly written wrong can be recognized. CONSTITUTION:A comparator 6 compares the address value which is outputted to an address bus by a DMA controller 1 in a memory writing cycle during the DMA transfer with the counted value of an address counter 7. Then the comparator 6 produces an error status signal to stop the operation of the controller 1 when no coincidence is obtained between said address value and counted value. The error status signal is held by an interruption latch 3 as an interruption signal to be applied to a microprocessor. At the same time, the error status signal is stored in a status register 4 so that the error occurrence information can be read out of the microprocessor. Thus it is possible to recognize the DMA writing address having an error and to enable the microprocessor to take a proper countermeasure.
JP62218367A 1987-09-01 1987-09-01 Dma control circuit Pending JPS6461847A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62218367A JPS6461847A (en) 1987-09-01 1987-09-01 Dma control circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62218367A JPS6461847A (en) 1987-09-01 1987-09-01 Dma control circuit

Publications (1)

Publication Number Publication Date
JPS6461847A true JPS6461847A (en) 1989-03-08

Family

ID=16718781

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62218367A Pending JPS6461847A (en) 1987-09-01 1987-09-01 Dma control circuit

Country Status (1)

Country Link
JP (1) JPS6461847A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009303391A (en) * 2008-06-13 2009-12-24 Masaaki Iwatani Disk coil
JP2010142035A (en) * 2008-12-12 2010-06-24 Honda Motor Co Ltd Stator coil of axial gap rotary electric machine
JP2010161928A (en) * 2010-04-26 2010-07-22 Honda Motor Co Ltd Stator coil of axial gap rotary electric machine
JP2011022781A (en) * 2009-07-15 2011-02-03 Mitsubishi Electric Corp Data transfer apparatus, data transfer method and data transfer program

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58129648A (en) * 1982-01-29 1983-08-02 Hitachi Ltd Data buffer device
JPS58159129A (en) * 1982-03-17 1983-09-21 Mitsubishi Electric Corp Dma controller of microcomputer system

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58129648A (en) * 1982-01-29 1983-08-02 Hitachi Ltd Data buffer device
JPS58159129A (en) * 1982-03-17 1983-09-21 Mitsubishi Electric Corp Dma controller of microcomputer system

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009303391A (en) * 2008-06-13 2009-12-24 Masaaki Iwatani Disk coil
JP2010142035A (en) * 2008-12-12 2010-06-24 Honda Motor Co Ltd Stator coil of axial gap rotary electric machine
JP2011022781A (en) * 2009-07-15 2011-02-03 Mitsubishi Electric Corp Data transfer apparatus, data transfer method and data transfer program
JP2010161928A (en) * 2010-04-26 2010-07-22 Honda Motor Co Ltd Stator coil of axial gap rotary electric machine

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