JPS6459697A - Nonvolatile semiconductor memory - Google Patents

Abstract

PURPOSE:To improve an action margin with the adjustment of the cell current value of a dummy cell by impressing an arbitrary potential to the erasing gate of a nonvolatile transistor for the dummy cell in a reference potential generating circuit. CONSTITUTION:When a prescribed potential is impressed to the erasing gate of a dummy cell DC in a reference potential generating circuit 15, the potential of a floating gate becomes larger than that of a main body memory cell CA. As this result, a cell current increases in the cell DC, and the value of a reference potential VREF generated in the circuit 15 decreases. At such a time, the values of a control gate potential and each capacity are set so that the value of the potential VREF may become the medium level of an input potential VSA 0 at the time of reading '0' and an input potential VSA 1 at the time of the reading '1', and thus, a sense margin in a sense amplifying circuit 14 becomes the maximum. In addition, at such a time, the speeds of the reading '0' and the reading '1' become the same, and the reliability of the action at the time of the reading data from the cell CA is improved.