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JPS6459448A - High speed transfer system - Google Patents

High speed transfer system

Info

Publication number
JPS6459448A
JPS6459448A JP21612587A JP21612587A JPS6459448A JP S6459448 A JPS6459448 A JP S6459448A JP 21612587 A JP21612587 A JP 21612587A JP 21612587 A JP21612587 A JP 21612587A JP S6459448 A JPS6459448 A JP S6459448A
Authority
JP
Japan
Prior art keywords
reception
data transmission
bus
address
address bus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP21612587A
Other languages
Japanese (ja)
Other versions
JP2527335B2 (en
Inventor
Satoshi Nagasaki
Yoshiyuki Uehara
Hirobumi Tatsuta
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
PFU Ltd
Original Assignee
Fujitsu Ltd
PFU Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd, PFU Ltd filed Critical Fujitsu Ltd
Priority to JP62216125A priority Critical patent/JP2527335B2/en
Publication of JPS6459448A publication Critical patent/JPS6459448A/en
Application granted granted Critical
Publication of JP2527335B2 publication Critical patent/JP2527335B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Information Transfer Systems (AREA)

Abstract

PURPOSE:To effectively quickly transfer data by providing a means which executes a mode where an address bus is used for data transmission and reception together with a data bus in the idle time after the access to a pertinent address of the address bus in case of continuous several-times data transmission and reception in one data transfer cycle. CONSTITUTION:The means is provided which executes the mode where the address bus is used for data transmission and reception together with the data bus in the idle time after the address access in the transfer cycle of the address bus in case of continuous several-times data transmission and reception in one transfer cycle corresponding to one address. That is, the mode where the idle time of the address bus is used to use the address bus for data transmission and reception in second and following data transmission and reception is newly provided in bus specifications. Thus, the data bus width and the address bus width are used in second and following data transmission and reception, and the idle time of the address bus is effectively used to shorten the transfer time.
JP62216125A 1987-08-29 1987-08-29 High-speed transfer method Expired - Fee Related JP2527335B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62216125A JP2527335B2 (en) 1987-08-29 1987-08-29 High-speed transfer method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62216125A JP2527335B2 (en) 1987-08-29 1987-08-29 High-speed transfer method

Publications (2)

Publication Number Publication Date
JPS6459448A true JPS6459448A (en) 1989-03-07
JP2527335B2 JP2527335B2 (en) 1996-08-21

Family

ID=16683650

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62216125A Expired - Fee Related JP2527335B2 (en) 1987-08-29 1987-08-29 High-speed transfer method

Country Status (1)

Country Link
JP (1) JP2527335B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1998019245A1 (en) * 1996-10-28 1998-05-07 I-O Data Device Inc. Data transfer method

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53132231A (en) * 1977-04-25 1978-11-17 Hitachi Ltd Control unit for data write-in
JPS6197767A (en) * 1984-10-18 1986-05-16 Toshiba Mach Co Ltd 9-16-bit parallel output circuit of microcomputer
JPS61220042A (en) * 1985-03-26 1986-09-30 Toshiba Corp Memory access control system

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53132231A (en) * 1977-04-25 1978-11-17 Hitachi Ltd Control unit for data write-in
JPS6197767A (en) * 1984-10-18 1986-05-16 Toshiba Mach Co Ltd 9-16-bit parallel output circuit of microcomputer
JPS61220042A (en) * 1985-03-26 1986-09-30 Toshiba Corp Memory access control system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1998019245A1 (en) * 1996-10-28 1998-05-07 I-O Data Device Inc. Data transfer method

Also Published As

Publication number Publication date
JP2527335B2 (en) 1996-08-21

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Legal Events

Date Code Title Description
S531 Written request for registration of change of domicile

Free format text: JAPANESE INTERMEDIATE CODE: R313532

R350 Written notification of registration of transfer

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LAPS Cancellation because of no payment of annual fees