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JPS6457850A - Digital signal transmission system - Google Patents

Digital signal transmission system

Info

Publication number
JPS6457850A
JPS6457850A JP62213935A JP21393587A JPS6457850A JP S6457850 A JPS6457850 A JP S6457850A JP 62213935 A JP62213935 A JP 62213935A JP 21393587 A JP21393587 A JP 21393587A JP S6457850 A JPS6457850 A JP S6457850A
Authority
JP
Japan
Prior art keywords
level
word synchronization
split
word
synchronization
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62213935A
Other languages
Japanese (ja)
Inventor
Satoshi Hirashima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP62213935A priority Critical patent/JPS6457850A/en
Publication of JPS6457850A publication Critical patent/JPS6457850A/en
Pending legal-status Critical Current

Links

Landscapes

  • Dc Digital Transmission (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE:To easily take bit synchronization and word synchronization at a receiver side, by converting a data part into a Split-Phase code, using a 4T for word synchronization and inserting same level signal consecutively for 3T during 4T period. CONSTITUTION:A data part is converted into a Split-Phase code causing positive polarity change with data '1' and negative polarity inversion with data '0' or vice versa. Assuming the minimum inverting interval of a digital data part be T, 4T is used for word synchronization, a 1st 1T is used for 1 level, 2nd-4th T as 0 level among the 4T and the 1st T is used for 0 level and the 2nd T-4th T are used for 1 level as word synchronizing pattern. In converting the digital data into the Split-Phase code, the same level signal only for 2T is generated at most consecutively. Thus, in inserting a signal consecutive for 3T as word synchronization and LR identification signal, the word synchronization is taken easily by the receiver side.
JP62213935A 1987-08-27 1987-08-27 Digital signal transmission system Pending JPS6457850A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62213935A JPS6457850A (en) 1987-08-27 1987-08-27 Digital signal transmission system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62213935A JPS6457850A (en) 1987-08-27 1987-08-27 Digital signal transmission system

Publications (1)

Publication Number Publication Date
JPS6457850A true JPS6457850A (en) 1989-03-06

Family

ID=16647484

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62213935A Pending JPS6457850A (en) 1987-08-27 1987-08-27 Digital signal transmission system

Country Status (1)

Country Link
JP (1) JPS6457850A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6393082B1 (en) 1997-11-06 2002-05-21 Nec Corporation Signal synchronism detecting circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6393082B1 (en) 1997-11-06 2002-05-21 Nec Corporation Signal synchronism detecting circuit

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