JPS645518B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a transmitting/receiving circuit for button and lamp information of a button telephone device or the like.

Accommodated in key telephone equipment, private branch exchanges, etc. that allow multiple subscribers to share 1 to 10 central office lines with 2 to 20 telephones, and also to make internal calls between these telephones. In multi-function terminals that provide a variety of advanced services through button operations or lamp dimming, various types of information such as button and lamp information are transmitted between the main device and the terminal in addition to conventional voice. , must be received.

On the other hand, with recent advances in LSI technology, storage program methods using central processing units such as microprocessors have become popular for controlling these main devices.

Conventionally, the scanning of button information and the sending of lamp information in this type of button telephone control circuit have been carried out through the input/output channel of the central processing unit, and the input/output commands for this purpose have been carried out according to the processing capacity of the central processing unit. At the same time, the software became complicated.

Furthermore, different clocks and buttons for the central processing unit and clocks for transmitting and receiving lamp information are often used, and for this reason, when input/output data from the central processing unit is transferred to the terminal, only one clock is used. It required storage in registers, which made the hardware complex.

An object of the present invention is to provide a button telephone control circuit that does not adversely affect the processing capacity of a central processing unit, software, etc., and has a simple hardware configuration.

According to the present invention, a clock generation circuit, a central processing circuit which receives the output of the clock generation circuit and is controlled so that a data bus and an address bus are periodically in a floating state, and a data bus of the central processing circuit; A storage circuit whose data input/output and address input are connected to the bus and address bus, respectively, and an address/output circuit of the central processing circuit.
a first gate circuit having an output connected to the bus and transmitting a desired address when the data bus is in a floating state; and a first gate circuit having an input connected to the data bus of the central processing circuit and transmitting a desired address when the data bus is in a floating state; a data distribution circuit that latches the output from the storage circuit, converts it into a desired form, and then distributes it to a plurality of outputs when the data is stored; and a plurality of buttons each having a data input connected to the output of the data distribution circuit. a telephone; a data editing circuit for converting the output from the plurality of button telephones into a desired form, the data outputs of the plurality of button telephones being respectively connected to a plurality of inputs; Each output is connected to the data bus of the central processing circuit, and the data bus of the central processing circuit is
a second circuit for sending the output of the data editing circuit to the data bus when the bus becomes floating;
A button telephone control circuit is obtained, characterized in that it is comprised of a gate circuit and a gate circuit.

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing an example of a conventional key telephone control circuit, and FIG. 2 is a time chart for explaining the operation of the conventional key telephone control circuit shown in FIG.

According to FIG. 1, the terminal address information output by central processing circuit 100 onto data bus 101 can be stored in first latch circuit 102. Referring to FIG. Next, the central processing circuit 100 also processes the data bus 1.
The lamp information outputted to 01 is similarly stored in the second latch circuit 103. The terminal address information 200 and lamp information stored in the first and second latch circuits 102 and 103 in this manner are determined by the first clock generation circuit 104.
During the period 201, the first selection circuit 105 and the second selection circuit 105
storage circuits 107 through the selection circuits 106 of
added to address and data inputs.
As a result, the lamp information stored in the second latch circuit 103 is stored in the memory circuit 107 at the address indicated by the terminal address information 200 stored in the first latch circuit 102. During a second period 202 shown in FIG. 2, terminal address information 203 from clock generation circuit 104 is applied to the address input of storage circuit 107 via first selection circuit 105. The lamp information stored in the memory circuit 107 by the central processing circuit 100 in this manner is the terminal address information 2 output by the clock generation circuit 104.
03 to the data output, and is applied to the input of the data distribution circuit 109 via the third selection circuit 108. The data distribution circuit 109 converts the lamp information output from the memory circuit 107 into a desired form, and then transmits the lamp information to the first, second, ... nth button telephones 11.
0, 111, and 112, respectively.

On the other hand, the first, second... and nth button telephones 1
Button information from 10, 111, and 112 is applied to a plurality of inputs of data editing circuit 113, respectively. The data editing circuit 113 is connected to each button telephone 11.
After converting the lamp information outputted from 0, 111, and 112 into a desired form, it is delivered to the second selection circuit 106. The lamp information thus obtained is stored in the storage circuit 107 during the third period 204 shown in FIG.
At this time, the clock generation circuit 104 stores the clock at the address indicated by the terminal address information 203 outputted through the first selection circuit 105. In this way, each button telephone 110, 11
The button information from 1 and 112 is sequentially stored in the storage circuit 107 in accordance with the terminal address information 203 output from the clock generation circuit. Next, the central processing circuit 100 passes the data bus 101 to the first latch circuit 1 as in the case of writing the lamp information.
The terminal address information 200 is sent to 02. 1st
The terminal address information 200 stored in the latch circuit 102 is applied to the address input of the storage circuit 107 via the first selection circuit 105 during a fourth period 205 shown in FIG. As a result, the button information obtained at the data output of the memory circuit 107 is
the third latch circuit 114 through the selection circuit 108 of
is stored in Therefore, the central processing circuit 100 can read the button information stored in the third latch circuit 114 by opening the gate circuit 115.

In this way, in the conventional button telephone control circuit, information is exchanged between the central processing circuit 100 and the memory circuit 107, and each button telephone 110, 111,
Since the information exchange between 112 and the memory circuit 107 is completely asynchronous, the period T determined by the clock generation circuit as shown in FIG.
A first period 201 in which lamp information is written from the central processing circuit 100 to the memory circuit 107;
A second period 202 for transmitting lamp information to the memory circuit 1 from each button telephone 110, 111, 112.
A third period 204 for importing button information to 07;
and a fourth period 205 in which button information is read from the memory circuit 107 to the central processing circuit 100, and the terminal address information 200 and lamp information from the central processing circuit 100 are stored in the first and second latch circuits. A method is used in which the button information from the circuit 107 is temporarily stored in each third latch circuit.

For this reason, many latch circuits and selection circuits as shown in FIG. 1 are required, and the central processing circuit 10
Main memory circuit 11 used for processing 0
In addition to 6, an extra memory circuit 107 is also required, which makes the hardware complicated.

Furthermore, the button information and the scanning lamp information are all sent through the input/output channel of the central processing unit 100, and input/output commands for this purpose reduce the processing capacity of the central processing unit 100 and require software. It was considered complicated.

FIG. 3 is a block diagram showing one embodiment of the present invention. Components having the same functions as those in FIG. 1 are indicated by the same symbols.

According to FIG. 3, one embodiment of the present invention includes a clock generation circuit 104 and a clock generation circuit 10.
A central processing circuit 100 to which a direct memory access (hereinafter referred to as DMA) request input is connected to the first output of 4, and a data bus and address bus 101, 300 of this central processing circuit 100.
a main memory circuit 116 whose data input/output and address input are respectively connected to the clock generating circuit 104; a first gate circuit 301 whose input is connected to the second output of the clock generating circuit 104 and whose output is connected to the address bus 300; , a data distribution circuit 109 whose input is connected to the data bus 101 of the central processing circuit 100, and a first, second, . Button telephone 110, 111, 1
12, and a data editing circuit 113 having a plurality of inputs connected to the data outputs of the first, second, . . . , and n-th button telephones 110, 111, 112, respectively.
And input to the output of this data editing circuit 113,
and second gate circuits 302 each having an output connected to the data bus 101 of the central processing circuit 100.

According to FIG. 3, the lamp information from the central processing circuit 100 is stored at a desired address in the main memory circuit 116 by a memory write command.

On the other hand, a DMA request signal is applied to the central processing circuit 100 by the clock generation circuit 104.
The bus and address buses 101 and 300 are controlled to be synchronously floating. At this time, address information from the clock generation circuit 104 is outputted to the address bus 300 via the first gate circuit 301. central processing circuit 10
0 data bus and address bus 101,
When 300 is in a floating state, one of two modes is executed as follows. 1st
In this mode, the address signal output by the first gate circuit 301 is sent to the main memory circuit 116.
The lamp information is read out to the data output of the main memory circuit 116 by being added to the address input of the main memory circuit 116. The lamp information thus obtained is sent to the data distribution circuit 109 via the data bus 101.
added to the input. The data distribution circuit 109 converts the lamp information output from the main memory circuit 116 into a desired form and then sends it to the first, second, .
On the other hand, the first, second... and n-th button telephones 11
Button information from 0, 111, and 112 is applied to a plurality of inputs of the data editing circuit 113, respectively. The data editing circuit 113 is connected to each button telephone 11.
After converting the lamp information output from 0, 111, and 112 into a desired form, the second gate circuit 302
send to the input of

In the second mode in which the data bus and address buses 101 and 300 of the central processing circuit 100 are in a floating state, button information from the data editing circuit 113 is sent to the second gate circuit 30.
2 onto data bus 101. The button information thus added to the data input of the main memory circuit 116 is stored at the address indicated by the address signal output by the first gate circuit 301.

As described above, the present invention simplifies the hardware configuration by employing the DMA method for transmitting and receiving button and lamp information between the key telephone and the main device.

Furthermore, according to the present invention, it is possible to scan button information and send out lamp information without using input/output commands, thereby improving the processing capacity of the central processing circuit 100 and increasing the software efficiency. It becomes possible to easily configure clothing.

FIG. 4 is a block diagram showing a specific example of the data editing circuit 113 shown in FIG. 3.

According to FIG. 4, each button telephone 11 shown in FIG.
Button information from 0, 111, and 112 is applied to multiple inputs of multiplex conversion circuit 400. These button information are sequentially time-division multiplexed by a multiplex conversion circuit 400 and then converted into parallel data by a serial/parallel conversion circuit 401. The button information for each button telephone obtained in this way is stored in the code circuit 4.
02 into a binary code and then sent to the data bus 101 shown in FIG.

FIG. 5 is a block diagram showing a specific example of the data distribution circuit 109 shown in FIG. 3.

According to FIG. 5, the main memory circuit 116 shown in FIG.
The lamp information read from the latch circuit 500
is stored in The lamp information thus obtained is converted into serial data by a parallel-to-serial conversion circuit 501 and then applied to the input of a demultiplexing circuit 502. The demultiplexer circuit 502 distributes the lamp information output by the parallel-to-serial converter circuit 501 to each of the key telephones 110, 111 and 112 connected to a plurality of outputs, respectively.

As described above, according to the present invention, it is possible to obtain a button telephone control circuit which has a simple hardware configuration and which does not reduce the processing power of the central processing circuit or complicate the software.

Generally, the data editing circuit 1 shown in FIG.
13. The data distribution circuit 109 shown in FIG. 5 includes a circuit for removing and inserting information for synchronization, respectively;
Although an interface circuit with the subscriber line and, in some cases, a power supply circuit, etc., are also required, they are not directly related to the present invention, so their explanation is omitted.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of a conventional button telephone control circuit, FIG. 2 is a time chart for explaining the operation of the button telephone control circuit shown in FIG. 1, and FIG. 3 is an embodiment of the present invention. A block diagram showing an example, FIG. 4 is the data editing circuit 11 shown in FIG.
FIG. 5 is a block diagram showing a specific example of the data distribution circuit 109 shown in FIG. 3. FIG. In the figure, 100 is a central processing circuit, 102, 1
03 and 114 are latch circuits, 104 is a clock generation circuit, 105, 106 and 108 are selection circuits, 107 and 116 are storage circuits, 109 is a data distribution circuit, 110, 111 and 112 are button telephones, 113 is a data editing circuit, 115,
301 and 302 represent gate circuits, respectively.

Claims (1)

[Claims] 1. A clock generation circuit, a central processing circuit which receives the output of the clock generation circuit and is controlled so that the data bus and address bus are periodically in a floating state, and the data bus and address bus of the central processing circuit. a memory circuit whose data input/output and address input are respectively connected to the bus; and a first memory circuit whose output is connected to the address bus of the central processing circuit and which sends out a desired address when the address bus is in a floating state. The input is connected to the gate circuit and the data bus of the central processing circuit, and when the data bus becomes floating, the output from the memory circuit is latched, converted into a desired form, and then distributed to multiple outputs. a plurality of button telephones each having a data input connected to an output of the data distribution circuit; and a data output of the plurality of button telephones having a data output connected to a plurality of inputs thereof respectively; a data editing circuit for converting the data into a desired form; an input is connected to the output of the data editing circuit; an output is connected to a data bus of the central processing circuit; and the data bus of the central processing circuit is in a floating state. and a second gate circuit that sends the output of the data editing circuit to the data bus when the button telephone control circuit is connected to the data bus.