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JPS6454523A - Detecting device for erroneous insertion of printed board - Google Patents

Detecting device for erroneous insertion of printed board

Info

Publication number
JPS6454523A
JPS6454523A JP62209291A JP20929187A JPS6454523A JP S6454523 A JPS6454523 A JP S6454523A JP 62209291 A JP62209291 A JP 62209291A JP 20929187 A JP20929187 A JP 20929187A JP S6454523 A JPS6454523 A JP S6454523A
Authority
JP
Japan
Prior art keywords
address
cpu
board
name code
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62209291A
Other languages
Japanese (ja)
Inventor
Teruo Nakagawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP62209291A priority Critical patent/JPS6454523A/en
Publication of JPS6454523A publication Critical patent/JPS6454523A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/10—Plc systems
    • G05B2219/11—Plc I-O input output
    • G05B2219/1113—Address setting
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/10—Plc systems
    • G05B2219/11—Plc I-O input output
    • G05B2219/1188—Detection of inserted boards, inserting extra memory, availability of boards

Landscapes

  • Debugging And Monitoring (AREA)

Abstract

PURPOSE:To eliminate the need of an address setting circuit, and to easily detect an erroneous insertion by detecting the mounting of a printed board, based on an access address, a name code, and a connector number and a name code which have been stored. CONSTITUTION:A CPU 1 outputs an assigned access address and executes an access to a printed board 11a. When the connector number and this address coincide, an address decoder 14 returns an acknowledge signal to the CPU 1. The CPU 1 stores its board name code in a memory 3. With respect to other boards 11b-11h, as well, the same thing is executed. When the board name codes are stored in the memory 3 with regard to all the boards, the CPU 1 compares the board name code which has been stored in advance in the memory 3, and the board name code which has been read. When results of comparison are different, they are displayed on a display device 9, or setting of the address, or a fact that the printed boards which have been connected to connectors 13a-13h are different is informed to a worker by an external apparatus 5, etc.
JP62209291A 1987-08-25 1987-08-25 Detecting device for erroneous insertion of printed board Pending JPS6454523A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62209291A JPS6454523A (en) 1987-08-25 1987-08-25 Detecting device for erroneous insertion of printed board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62209291A JPS6454523A (en) 1987-08-25 1987-08-25 Detecting device for erroneous insertion of printed board

Publications (1)

Publication Number Publication Date
JPS6454523A true JPS6454523A (en) 1989-03-02

Family

ID=16570512

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62209291A Pending JPS6454523A (en) 1987-08-25 1987-08-25 Detecting device for erroneous insertion of printed board

Country Status (1)

Country Link
JP (1) JPS6454523A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04120129U (en) * 1991-04-04 1992-10-27 三菱電機株式会社 Control device
US7133108B2 (en) 2000-12-08 2006-11-07 Hitachi, Ltd. Liquid crystal display device
JP2009009449A (en) * 2007-06-29 2009-01-15 Nec Commun Syst Ltd Circuit package apparatus and circuit package fault evasion method

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04120129U (en) * 1991-04-04 1992-10-27 三菱電機株式会社 Control device
US7133108B2 (en) 2000-12-08 2006-11-07 Hitachi, Ltd. Liquid crystal display device
US7456926B2 (en) 2000-12-08 2008-11-25 Hitachi, Ltd. Liquid crystal display device
US7826028B2 (en) 2000-12-08 2010-11-02 Hitachi, Ltd. Liquid crystal display device
JP2009009449A (en) * 2007-06-29 2009-01-15 Nec Commun Syst Ltd Circuit package apparatus and circuit package fault evasion method

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