JPS6453454A - Bipolar transistor and manufacture thereof - Google Patents
Bipolar transistor and manufacture thereofInfo
- Publication number
- JPS6453454A JPS6453454A JP12884588A JP12884588A JPS6453454A JP S6453454 A JPS6453454 A JP S6453454A JP 12884588 A JP12884588 A JP 12884588A JP 12884588 A JP12884588 A JP 12884588A JP S6453454 A JPS6453454 A JP S6453454A
- Authority
- JP
- Japan
- Prior art keywords
- polycrystalline silicon
- grow
- film
- window
- emitter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract 4
- 229910052581 Si3N4 Inorganic materials 0.000 abstract 2
- 238000005530 etching Methods 0.000 abstract 2
- 238000000034 method Methods 0.000 abstract 2
- 239000004065 semiconductor Substances 0.000 abstract 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract 2
- 239000000758 substrate Substances 0.000 abstract 2
- 229910052785 arsenic Inorganic materials 0.000 abstract 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 abstract 1
- 238000005468 ion implantation Methods 0.000 abstract 1
- 238000001459 lithography Methods 0.000 abstract 1
Landscapes
- Bipolar Transistors (AREA)
Abstract
PURPOSE:To form both a base region and an emitter region so as to be selfaligned with a first window, so that the base region and the emitter region are made small in area by a method wherein a sidewall is formed inside a first window opened through a lithography technique. CONSTITUTION:A first polycrystalline silicon 6 and a first insulating 5, which are formed on a semiconductor substrate that comprises an n<+>-type buried layer 2 and an n-type epitaxial layer 3 formed on a p-type semiconductor substrate 1, are successively subjected to an anisotropic etching for the opening of a first window 9. The exposed surface of the n-type epitaxial layer 3 is oxidized and a silicon nitride film is subjected to etching so as to remove a first side wall 9a. Next, a second polycrystalline silicon film 12 is made to grow. A sixth insulating film 17 formed of the same silicon nitride film as a second side wall 14 is made to grow to be excellent in a step coverage, thereafter a third polycrystalline silicon film 19 is made to grow, and an emitter is formed through the ion-implantation of arsenic. The polycrystalline silicon film 19 is selectively etched, so that a collector contact opening 20, a base contact opening 21, or the like are provided.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13724987 | 1987-05-29 | ||
| JP62-137249 | 1987-05-29 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6453454A true JPS6453454A (en) | 1989-03-01 |
| JP2540912B2 JP2540912B2 (en) | 1996-10-09 |
Family
ID=15194252
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63128845A Expired - Fee Related JP2540912B2 (en) | 1987-05-29 | 1988-05-25 | Bipolar transistor and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2540912B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0233930A (en) * | 1988-07-25 | 1990-02-05 | Hitachi Ltd | semiconductor equipment |
| US5599723A (en) * | 1993-12-22 | 1997-02-04 | Nec Corporation | Method for manufacturing bipolar transistor having reduced base-collector parasitic capacitance |
| US8716096B2 (en) | 2011-12-13 | 2014-05-06 | International Business Machines Corporation | Self-aligned emitter-base in advanced BiCMOS technology |
-
1988
- 1988-05-25 JP JP63128845A patent/JP2540912B2/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0233930A (en) * | 1988-07-25 | 1990-02-05 | Hitachi Ltd | semiconductor equipment |
| US5599723A (en) * | 1993-12-22 | 1997-02-04 | Nec Corporation | Method for manufacturing bipolar transistor having reduced base-collector parasitic capacitance |
| US8716096B2 (en) | 2011-12-13 | 2014-05-06 | International Business Machines Corporation | Self-aligned emitter-base in advanced BiCMOS technology |
| US8916952B2 (en) | 2011-12-13 | 2014-12-23 | International Business Machines Corporation | Self-aligned emitter-base in advanced BiCMOS technology |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2540912B2 (en) | 1996-10-09 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |