JPS6452300A - Semiconductor memory device - Google Patents
Semiconductor memory deviceInfo
- Publication number
- JPS6452300A JPS6452300A JP62208092A JP20809287A JPS6452300A JP S6452300 A JPS6452300 A JP S6452300A JP 62208092 A JP62208092 A JP 62208092A JP 20809287 A JP20809287 A JP 20809287A JP S6452300 A JPS6452300 A JP S6452300A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- selecting signal
- screening test
- test
- high level
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Techniques For Improving Reliability Of Storages (AREA)
- Semiconductor Memories (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
- Dram (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
PURPOSE:To make memory cells into a selective condition in a lump, to easily increase the number of the selections of respective memory cells in a screening test, such as a burn-in, and to improve the efficiency of the test by making the logical sum of the selecting signal and the collective selecting signal of an address decoder into the selecting signal of a word line. CONSTITUTION:The selecting signal from a low address decoder 2 and a collective selecting signal AS supplied from a screening test machine are inputted to a selecting means 3 consisting of an OR gate circuit. In the screening test, the low level and the high level of the signal AS are repeated in accordance with a memory cycle. When the signal AS becomes the high level, the outputs of the means 3 are all made into the high level regardless of the output of the decoder 2. Accordingly, in the screening test, all the memory cells can be made into the selective condition at a time, and the efficiency of the test is improved.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62208092A JPS6452300A (en) | 1987-08-24 | 1987-08-24 | Semiconductor memory device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62208092A JPS6452300A (en) | 1987-08-24 | 1987-08-24 | Semiconductor memory device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6452300A true JPS6452300A (en) | 1989-02-28 |
Family
ID=16550506
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62208092A Pending JPS6452300A (en) | 1987-08-24 | 1987-08-24 | Semiconductor memory device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6452300A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0250473A (en) * | 1988-08-12 | 1990-02-20 | Fujitsu Ltd | Address scan circuit |
| JPH0335491A (en) * | 1989-06-30 | 1991-02-15 | Toshiba Corp | Semiconductor memory device |
| JPH04225182A (en) * | 1990-12-26 | 1992-08-14 | Toshiba Corp | Semiconductor memory |
| US5267212A (en) * | 1990-10-23 | 1993-11-30 | Oki Electric Industry Co., Ltd. | Random access memory with rapid test pattern writing |
| US5267209A (en) * | 1990-09-14 | 1993-11-30 | Oki Electric Industry Co., Ltd. | EEPROM programming method |
| JPH0793995A (en) * | 1993-09-24 | 1995-04-07 | Nec Corp | Semiconductor memory device |
| JP2015064921A (en) * | 2013-08-26 | 2015-04-09 | 株式会社半導体エネルギー研究所 | Semiconductor device and manufacturing method of semiconductor device |
-
1987
- 1987-08-24 JP JP62208092A patent/JPS6452300A/en active Pending
Cited By (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0250473A (en) * | 1988-08-12 | 1990-02-20 | Fujitsu Ltd | Address scan circuit |
| JPH0335491A (en) * | 1989-06-30 | 1991-02-15 | Toshiba Corp | Semiconductor memory device |
| US6771544B2 (en) | 1990-09-14 | 2004-08-03 | Oki Electric Industry Co., Ltd. | EEPROM writing method |
| US6392933B1 (en) | 1990-09-14 | 2002-05-21 | Oki Electric Industry Co., Ltd. | EEPROM erasing method |
| US5267209A (en) * | 1990-09-14 | 1993-11-30 | Oki Electric Industry Co., Ltd. | EEPROM programming method |
| US7031197B2 (en) | 1990-09-14 | 2006-04-18 | Oki Electric Industry Co., Ltd. | EEPROM writing and reading method |
| US6744677B2 (en) | 1990-09-14 | 2004-06-01 | Oki Electric Industry Co., Ltd. | EEPROM erasing method |
| US6459623B1 (en) | 1990-09-14 | 2002-10-01 | Oki Electric Industry Co., Ltd. | EEPROM erasing method |
| US5267212A (en) * | 1990-10-23 | 1993-11-30 | Oki Electric Industry Co., Ltd. | Random access memory with rapid test pattern writing |
| US6307796B1 (en) | 1990-12-26 | 2001-10-23 | Kabushiki Kaisha Toshiba | Dynamic random access memory |
| US6381186B1 (en) | 1990-12-26 | 2002-04-30 | Kabushiki Kaisha Toshiba | Dynamic random access memory |
| US6317366B1 (en) | 1990-12-26 | 2001-11-13 | Kabushiki Kaisha Toshiba | Dynamic random access memory |
| JPH04225182A (en) * | 1990-12-26 | 1992-08-14 | Toshiba Corp | Semiconductor memory |
| JPH0793995A (en) * | 1993-09-24 | 1995-04-07 | Nec Corp | Semiconductor memory device |
| JP2015064921A (en) * | 2013-08-26 | 2015-04-09 | 株式会社半導体エネルギー研究所 | Semiconductor device and manufacturing method of semiconductor device |
| JP2019071481A (en) * | 2013-08-26 | 2019-05-09 | 株式会社半導体エネルギー研究所 | Semiconductor device and semiconductor device manufacturing method |
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