JPS6452293A - Memory built-in semiconductor integrated circuit - Google Patents
Memory built-in semiconductor integrated circuitInfo
- Publication number
- JPS6452293A JPS6452293A JP62208094A JP20809487A JPS6452293A JP S6452293 A JPS6452293 A JP S6452293A JP 62208094 A JP62208094 A JP 62208094A JP 20809487 A JP20809487 A JP 20809487A JP S6452293 A JPS6452293 A JP S6452293A
- Authority
- JP
- Japan
- Prior art keywords
- rom
- refreshing
- cycle
- capacity
- enlargement
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title 1
- 238000005265 energy consumption Methods 0.000 abstract 2
- 238000007689 inspection Methods 0.000 abstract 1
- 239000000523 sample Substances 0.000 abstract 1
Landscapes
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
- Dram (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
PURPOSE:To decrease the energy consumption of a single chip microcomputer for an IC card and to attain the enlargement of capacity by integrating a P-ROM with small capacity and a dynamic RAM and refreshing control circuit with large capacity on the same chip, and refreshing them based on the refreshing cycle stored in the ROM. CONSTITUTION:A ROM 8 storing an action program, electrically erasable P-ROM 10 to store the information of a personal identification code, etc., a dynamic RAM 11 and a refreshing control circuit 20 are provided on the same chip. The allowable refreshing cycle of a RAM 11 is measured by a probe inspection, and the measured value is written to the register in the P-ROM 10. Thus, the refreshment is executed with the optimum cycle for every microcomputer. For this reason, the energy consumption at the time of a standby is suppressed to a minimum, and the enlargement is attained.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62208094A JPS6452293A (en) | 1987-08-24 | 1987-08-24 | Memory built-in semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62208094A JPS6452293A (en) | 1987-08-24 | 1987-08-24 | Memory built-in semiconductor integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6452293A true JPS6452293A (en) | 1989-02-28 |
Family
ID=16550536
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62208094A Pending JPS6452293A (en) | 1987-08-24 | 1987-08-24 | Memory built-in semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6452293A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03209691A (en) * | 1989-12-13 | 1991-09-12 | Internatl Business Mach Corp <Ibm> | Method of giving reproducing pulse to data processing circuit, bit encode data memory device and memory array of memory card |
| WO1996028825A1 (en) * | 1995-03-15 | 1996-09-19 | Hitachi, Ltd. | Semiconductor memory |
-
1987
- 1987-08-24 JP JP62208094A patent/JPS6452293A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03209691A (en) * | 1989-12-13 | 1991-09-12 | Internatl Business Mach Corp <Ibm> | Method of giving reproducing pulse to data processing circuit, bit encode data memory device and memory array of memory card |
| WO1996028825A1 (en) * | 1995-03-15 | 1996-09-19 | Hitachi, Ltd. | Semiconductor memory |
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