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JPS6451525A - Arithmetic circuit - Google Patents

Arithmetic circuit

Info

Publication number
JPS6451525A
JPS6451525A JP20866287A JP20866287A JPS6451525A JP S6451525 A JPS6451525 A JP S6451525A JP 20866287 A JP20866287 A JP 20866287A JP 20866287 A JP20866287 A JP 20866287A JP S6451525 A JPS6451525 A JP S6451525A
Authority
JP
Japan
Prior art keywords
decrement
zero
decision part
data input
decision
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP20866287A
Other languages
Japanese (ja)
Inventor
Masahiro Wakamori
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP20866287A priority Critical patent/JPS6451525A/en
Publication of JPS6451525A publication Critical patent/JPS6451525A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To increase operation speed by providing a zero decision part and a one decision part and executing a decrement processing and a zero decision processing in parallel. CONSTITUTION:If an operation data input 9 is '1' when a zero decision enable signal 2 is enable and a decrement enable signal 1 is decrement-enable, a decrement result becomes zero, and therefore the one decision part action designation signal is outputted and the one decision part 10 decides whether an operation data input 9 is '1' or not. If the operation data input 9 is '0' when the decrement enable signal 1 is decrement-disable, a decrement result 15 becomes '0', and a zero decision part action instructing signal 8 is outputted. The zero decision part 11 decides whether the operation data input 9 is equal to '0' or not and a decrementer 12 outputs the data input 9 to the 15. Thus, the zero decision processing of the one decision part 10 and the zero decision part 11, and the decrement processing of the decrementer 12 can be executed in parallel, whereby action speed can be speeded up.
JP20866287A 1987-08-21 1987-08-21 Arithmetic circuit Pending JPS6451525A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20866287A JPS6451525A (en) 1987-08-21 1987-08-21 Arithmetic circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20866287A JPS6451525A (en) 1987-08-21 1987-08-21 Arithmetic circuit

Publications (1)

Publication Number Publication Date
JPS6451525A true JPS6451525A (en) 1989-02-27

Family

ID=16559971

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20866287A Pending JPS6451525A (en) 1987-08-21 1987-08-21 Arithmetic circuit

Country Status (1)

Country Link
JP (1) JPS6451525A (en)

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