JPS6450490U - - Google Patents
Info
- Publication number
- JPS6450490U JPS6450490U JP14544887U JP14544887U JPS6450490U JP S6450490 U JPS6450490 U JP S6450490U JP 14544887 U JP14544887 U JP 14544887U JP 14544887 U JP14544887 U JP 14544887U JP S6450490 U JPS6450490 U JP S6450490U
- Authority
- JP
- Japan
- Prior art keywords
- appropriate number
- motherboard
- connectors
- chassis
- connector
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Mounting Of Printed Circuit Boards And The Like (AREA)
Description
第１図は本考案に係る装置の一実施例を示す斜
視図である。第２図は第１図における主要部分を
断面して示した拡大平面図である。第３図は従来
の装置を示す斜視図である。
２３……シヤーシ、２５……マザーボード、２
７……ドータボード、２９，３１……コネクタ、
３３……外壁部、３５，３７，３９……絶縁層、
４１，４３……導体層、４７，４９……接続ピン
。
FIG. 1 is a perspective view showing an embodiment of the device according to the present invention. FIG. 2 is an enlarged plan view showing a cross section of the main part in FIG. 1. FIG. 3 is a perspective view of a conventional device. 23... chassis, 25... motherboard, 2
7... Daughter board, 29, 31... Connector,
33... Outer wall part, 35, 37, 39... Insulating layer,
41, 43... Conductor layer, 47, 49... Connection pin.
Claims (1)
壁部の内面側に適数層の絶縁層を介して適数の導
体層を備えた構成となし、前記シヤーシに保持さ
れる複数のドータボードに備えたコネクタを嵌込
自在な適数のコネクタを前記マザーボードの内側
面に固定し、このマザーボード側のコネクタに備
えた適数の保持ピンを前記導体層に接続して設け
ると共に各接続ピンを絶縁層に支持してなること
を特徴とする電子機器実装装置。 A motherboard mounted on a box-shaped chassis is configured to have an appropriate number of conductor layers on the inner surface of an outer wall through an appropriate number of insulating layers, and connectors are provided on a plurality of daughter boards held on the chassis. An appropriate number of connectors that can be freely fitted are fixed to the inner surface of the motherboard, and an appropriate number of holding pins provided on the connector on the motherboard are connected to the conductive layer, and each connecting pin is supported on an insulating layer. An electronic device mounting device characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14544887U JPS6450490U (en) | 1987-09-25 | 1987-09-25 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14544887U JPS6450490U (en) | 1987-09-25 | 1987-09-25 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6450490U true JPS6450490U (en) | 1989-03-29 |
Family
ID=31414047
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14544887U Pending JPS6450490U (en) | 1987-09-25 | 1987-09-25 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6450490U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0666085U (en) * | 1993-02-26 | 1994-09-16 | 株式会社東芝 | Printed circuit board unit |
-
1987
- 1987-09-25 JP JP14544887U patent/JPS6450490U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0666085U (en) * | 1993-02-26 | 1994-09-16 | 株式会社東芝 | Printed circuit board unit |
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