JPS644698B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an automatic gain control circuit, and particularly to an automatic gain control circuit applied to a receiving apparatus having a demodulator that receives and demodulates a data signal such as a facsimile signal.

Generally, such an automatic gain control circuit includes a variable gain amplifier and a loop filter that generates a gain control signal to control the gain of the variable gain amplifier, and supplies an automatically gain-controlled output signal to a demodulator. The loop filter typically provides a gain control signal to the variable gain amplifier at a constant loop gain based on a signal level error signal formed by, for example, full-wave rectification of the output of the variable gain amplifier and comparing it with a reference value. This stabilizes the level of the output signal.

Prior to receiving the data signal, the data signal receiving device executes a predetermined training sequence defined in, for example, the Consultative Committee for International Telegraph and Telephone (CCITT) recommendations V.27bis/ter or V.29. As is well known, in this training mode,
First, the process begins with binary symbol alternation and random signal reception, and then shifts to multilevel symbol random signal reception. Therefore, the change in the transmission spectrum due to the transition from the binary symbol mode to the multi-level symbol mode is affected by the line characteristics, and as a result, the level of the received signal fluctuates. However, in principle, the signal should not fluctuate after being completely equalized. Furthermore, in the transmission of multilevel symbols, the level of the received signal varies depending on the transmission pattern of the symbol, including the data reception mode.

In actual lines, especially telephone lines, the level fluctuations in the received signal vary from connection to connection, and also change over time, making them extremely noticeable. In addition to such fluctuations in line characteristics, level fluctuations also occur due to the following causes. For example, in an amplitude modulation method such as an orthogonal amplitude modulation method in which the carrier wave amplitude changes in multilevel symbol transmission, level fluctuations may occur due to a biased symbol transmission pattern. This level fluctuation can be prevented to some extent by scrambling the data at the transmitting end or by designing the time constant of the loop filter in the automatic gain control circuit included in the receiving device to be sufficiently large, but it is not completely possible. Further, depending on the symbol transmission pattern, although the transmission level does not change, the spectrum shape may change.
In such cases, the frequency characteristics (attenuation characteristics) of the telephone line are often quite uneven;
Changes in the spectral shape are affected by this non-uniformity and appear as level fluctuations in the received signal. This can also be dealt with by data scrambling or a large time constant of the loop filter, but this cannot effectively and immediately respond to the transition from binary symbols to multi-value symbols in the training sequence as described above. In particular, in the above-mentioned CCITT Recommendation V.29, the binary symbol pattern in the training sequence has a DC component, while in data mode multi-level symbol transmission there is virtually no DC component, resulting in large spectral changes. As a result, the level of the received signal fluctuates.

In this way, the level of the received signal may fluctuate depending on the line characteristics, but in a demodulator or modem (MODEM) with an automatic equalizer (also called an automatic adaptive equalizer), the level of the received signal may vary depending on the line characteristics. Since the line characteristics are almost completely equalized, it is desirable that the automatic gain control circuit maintain a constant gain without responding to such level fluctuations of the received signal. However, even in such cases, conventional automatic gain control circuits try to follow the level fluctuations of the received signal and keep it constant, which results in temporary fluctuations in the output level of the automatic equalizer. Become.
This fluctuation will eventually be absorbed by the automatic equalizer through its adaptive operation, but until then, the performance of the entire demodulator will temporarily deteriorate, especially due to bit errors. rate will increase.
This occurs particularly when transitioning to data mode after the initial training of the demodulator, but it will take some time for the demodulator to return to full performance. Therefore, there is a drawback that the effective training period becomes longer.

The present invention solves these drawbacks of the prior art,
The purpose of this invention is to provide an automatic gain control circuit that is not affected by line characteristics or symbol transmission patterns.

Specifically, the present invention eliminates the influence of spectral changes when transitioning from binary symbols to multilevel symbols in the demodulator training sequence;
It is an object of the present invention to provide an automatic gain control circuit that is independent of symbol transmission patterns in data reception mode.

These objectives are achieved by an automatic gain control circuit according to the present invention as follows. That is, the circuit includes a first error detection circuit that generates a first signal representative of the gain error of the variable gain amplifier based on the center tap gain of the automatic equalizer; A gain control signal is provided to the variable gain amplifier, thereby stabilizing the level of the output signal.

In addition to the first error detection circuit, this automatic gain control circuit also includes a second error detection circuit that generates a second signal representing an error in the level of the output signal, and a first error detection circuit.
and switching means for selectively taking the second state and transitioning from the first state to the second state in response to a predetermined point in time during the training period of the automatic equalizer; In the first state, the second error detection circuit is connected to the loop filter and the second signal is supplied thereto, and in the second state, the first error detection circuit is connected to the loop filter. a first signal to the loop filter with a high loop gain in response to the second signal;
A gain control signal is provided to the variable gain amplifier with a low loop gain in response to the signal.

Next, embodiments of an automatic gain control circuit according to the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 shows an example in which an automatic gain control circuit according to the present invention is applied to a receiving device including a demodulator for a signal such as a facsimile signal. In the same figure,
This receiving device has a bandpass filter BPF connected to a terminal 10 that receives a line signal such as a facsimile signal from a line, and this filter removes noise in an unnecessary band included in the line signal and outputs it to a lead 12. .

Lead 12 is equipped with an automatic gain control circuit according to the present invention.
An AGC is connected, and this is a circuit that converts the input signal A on the lead 12, which has an undefined level, into an output signal B, which has a constant level, and outputs it to the lead 14.

Lead 14 is applied to one input of the multiplier MLTI, and the other input 16 is connected to the carrier oscillator.
OSC is connected. Multiplier MLTI output 18
A low-pass filter LPF is connected to , and its output 2
0 is connected to the automatic equalizer AAE. The carrier wave oscillator OSC generates the carrier wave of the received line signal e ^j 〓c ^t
A carrier wave e ^j (ω _{c t + Θ) whose phase is shifted by Θ is generated, and in conjunction with a multiplier MLTI and a filter LPF, the carrier wave e j (ω c} t + Θ) is
The signal B of No. 4 is demodulated into the baseband signal r _k . The automatic equalizer AAE is an equalizer that automatically adapts and equalizes line signals to the characteristics of the receiving line.

The output 22 of the equalizer AAE is connected to a quantizer QZ, which determines and quantizes the symbols contained in the line signal from the output y _k of the equalizer AAE.

The output 22 of the equalizer AAE and the output 24 of the quantizer QZ are input to a subtracter SUBI, which produces a difference signal e _k between the signal y _k on the lead 22 and the signal a^ _k on the lead 24.
is output to lead 26 and input to equalizer AAE. This is used for convergence of the equalizer AAE.

In this embodiment, the signal received at the terminal 10 from the line is, for example, a scrambled, differentially encoded, and quadrature amplitude modulated signal at the transmitting end. That is, data signals such as facsimile signals are averaged and randomized so that the symbol transmission pattern is not biased.
A scrambled bit stream is formed and the phase components of the bit stream are then differentially encoded to remove carrier phase ambiguities. Next, this is passed through a low-pass filter to shape the frequency spectrum of the symbol, and this baseband signal is used to calculate the frequency f _c (f _c =
The carrier wave e ^j 〓c ^t of ω _c /2π) is modulated, frequency components in unnecessary bands are removed by a band filter or a low-pass filter, and the signal is sent to the line. Note that the modulation method may be, for example, one-dimensional or two-dimensional amplitude modulation, or may be a two-dimensional modulation method or phase modulation method.

Since the received signal at the terminal 10 is thus differentially encoded and scrambled, the receiving apparatus shown in FIG. 1 is provided with a differential decoder DD and a descrambler DS. The differential decoder DD forms a bit stream from the symbols contained in the quantized signal _ak . Its output 28 is connected to a descrambler DS which has an inverse function to the scrambler at the transmitting end and recovers a data signal from the bit stream on lead 28 and outputs it to an output terminal 30.

By the way, a conventional automatic gain control circuit generally has a configuration as shown in FIG. 2, for example. As is well known, automatic gain control circuit is a variable gain amplifier.
It is composed of a VGA, a signal level error detector 100, and a loop filter 102. The signal level error detector 100 has a full-wave rectifier FWR and a subtracter SUB2 that generates a difference between its output and a reference level REF. Instead of full wave rectifier FWR,
Square circuits, half-wave rectifiers or peak detectors may also be used. The signal level error is output to the output 104 of the subtracter SUB2, which is passed through the loop filter 1.
02 multiplier MLT2. The loop filter 102 includes an integrator IG in addition to the multiplier MLT2.
It also has

When the integrator IG is a first-order system, its operation is expressed as 1/sT, where s is the Laplace operator and T is the time constant, as shown in the equivalent circuit in Figure 3A, and is applied to the multiplier MLT2. Let α be the loop gain obtained by
The transfer function of the loop filter 102 is 1/s(T/α) as shown in the equivalent circuit of FIG. Therefore, the time constant of the loop filter 102 can be equivalently considered to be inversely proportional to the loop gain α.
Therefore, if an automatic gain control circuit with a large loop gain α is used, the time constant will be small and the response will be quick; if vice versa, the response will be slow.

By the way, the automatic equalizer AAE is designed to handle not only line distortion, but also sample phase error in timing detection, phase error in carrier detection, and automatic gain control circuit.
It is also possible to absorb AGC gain errors. According to the present invention, the gain error of the automatic gain control circuit AGC is determined from the tap gain of the equalizer AAE.

If the gain of the gain control circuit AGC increases for some reason, the levels of the signals B and r _k will increase, and the level of the output y _k of the equalizer AAE will also increase. Therefore, by the difference signal e _k , the equalizer AAE is
The tap gain of is corrected, and the absolute value of the gain of each tap is decreased. This allows equalizer AAE
The level of the output signal y _k decreases to its original level. Similarly, in the reverse case, the absolute value of the gain of each tap of the equalizer AAE increases, and the level of the signal _yk increases to its original level.

In the case of general line characteristics, the tap gain of the equalizer AAE is such that the absolute value of the gain C _p of the center tap is the maximum, and the absolute value of the gain of each tap decreases rapidly as the distance from the center tap increases. is well known. Furthermore, the central tap gain C _p is not affected much by the line characteristics. Therefore, the automatic gain control circuit is controlled by the absolute value of the central tap gain of the automatic equalizer AAE.
The AGC gain error can be found. equalizer
AAE decreases the absolute value |C _p | of the central tap gain when the gain of the gain control circuit AGC increases, and increases |C _p | when the gain decreases.

According to the invention, automatic gain control of the automatic gain control circuit AGC is performed based on a signal representative of the central tap gain C _p supplied to the automatic gain control circuit AGC by lead 34 from the automatic equalizer AAE;
The gain error is calculated from the center tap gain C _p of the equalizer AAE. As a result, |C _p | is kept constant.

FIG. 4 shows an embodiment of an automatic gain control circuit that performs automatic gain control using the central tap gain C _p of the automatic equalizer AAE. This automatic gain control circuit AGC is
Variable gain amplifier VGA and amplification factor error detector 20
0 and a loop filter 202. The loop filter 200 has an accumulator GAIN, a subtracter SUB51, and a multiplier MLT51.
It functions as the following integrating circuit. As shown, the amplification error detector 200 includes two multipliers MLT53 and MLT54, an adder ADD51, and a subtracter SUB52.

The amplification factor error detector 200 is an automatic equalizer AAE.
A center tap gain C _p is received by lead 34 from the center tap gain C p . This is the lead 34a as shown in FIG.
The lead 34b receives the real part Re (C _p ) of the central tap gain, and the imaginary part Im (C _p ) of the central tap gain. lead 3
4a and 34b are supplied to two inputs of multipliers MLT53 and MLT54, respectively, and outputs 204 and 206 of both multipliers are supplied to adder ADD51.
is fed to the two inputs of the adder
The square of the absolute value of the central tap gain |C _p | ² is output at the output 208 of the ADD 51 . Subtractor SUB5
2 outputs to lead 210 an amplification factor error signal GE representing the difference between this and the reference value REFO.

The error signal GE is supplied to one input of the multiplier MLT51, and the other input 212 is supplied with the loop gain α _p . Output 214 of multiplier MLT51
is connected to subtractor SUB51, and subtractor SUB51
The output 216 of is connected to the accumulator GAIN. Output 218 of accumulator GAIN
is input to the variable gain amplifier VGA and also fed back to the subtracter SUB51.

When the level of the accumulator GAIN is at an ideal value (target value), the central tap gain C _p of the equalizer AAE is |C _p | ² = REFO, so
The error signal GE is zero. Therefore, the system maintains this state. If the output level of the accumulator GAIN is greater than the ideal value, the variable gain amplifier
The amplification factor of the VGA increases, and the automatic equalizer AAE changes the tap gain to absorb or equalize this. As a result, |C _p | ² becomes smaller than the reference value REFO, and GE takes a positive value. This positive value GE is multiplied by the loop gain α _p by the multiplier MLT51, and subtracted from the output level of the accumulator GAIN by the subtractor SUB51, so that
As a result, the output level of the accumulator GAIN decreases and approaches the ideal value. Furthermore, when the output level of the accumulator GAIN is smaller than the ideal value, the opposite operation occurs and GE becomes negative, and the output level of the accumulator GAIN increases and approaches the ideal value.

As can be seen from the previous explanation, the automatic gain control circuit AGC shown in Figure 4 includes a low-pass filter LPF and an automatic equalizer in the automatic gain control feedback loop.
These elements have relatively large delays, including the AAE (FIG. 1). Since this feedback loop requires relative stability, it is difficult to increase the loop gain. This agrees with the requirement that it is generally desirable for a demodulator to have a large time constant for automatic gain control in data reception mode. However, in the initial training mode of the demodulator, the level of the input signal A is unstable and its range is wide. Moreover, since it is required to follow the input signal level within a short period of time, it is desirable that the time constant of automatic gain control be small at the initial stage of training.

An embodiment of the automatic gain control circuit AGC according to the present invention that satisfies this requirement will be described with reference to FIG.
In this figure, structural elements similar to those in the circuit of FIG. 4 are designated by the same reference numerals. This circuit includes a signal level error detector 300, a loop filter 302, and selectors SEL1 and SEL2 in addition to the amplification factor error detector 200 similar to that shown in FIG. Also, the input circuit for the received signal A is analog. digital converter
An ADC is provided, which receives an analog signal A
is converted into a corresponding digital signal A1 and supplied to each circuit within the device. This is because each circuit in the device has a function suitable for being implemented by a digital circuit, and therefore each circuit is implemented using a digital element in this embodiment. Therefore, if it is implemented using an analog circuit, a converter ADC is used.
is not necessary.

The signal level error detector 300 is a multiplier MLT6
5 and a subtractor SUB63, the output 14 of the variable gain amplifier VGA is connected to its two inputs,
Output 304 is connected to one input of subtractor SUB63. The other input of the subtracter SUB63 is supplied with the reference level REF1.

Output 306 of subtractor SUB63 is selector SEL
1, and the output 208 of the amplifier error detector 200 is connected to the contact 0. The switching arm of selector SEL1 is connected by lead 308 to the input of multiplier MLT51 of loop filter 302. The other input 212 of the multiplier MLT51 is connected to the switching arm of the selector SEL22, and the loop gain α is connected to the contact 0 of the selector.
1, and the same α0 is supplied to contact 0. These loop gains are set so that α1 is sufficiently larger than α0.

In the loop filter 302, a multiplier MLT66 is connected between the multiplier MLT51 and the subtracter SUB51, and the output 2 of the accumulator GAIN is also connected to this multiplier MLT66.
The loop filter 202 has the same function as the loop filter 202 in FIG.

Two selectors SEL1 and SEL2 receive a signal INITIAL supplied from a carrier detector (not shown).
controlled by. The signal INITIAL assumes a logic "1" state due to carrier detection at the first stage of the training sequence of the demodulator, and after a predetermined time elapses after the carrier detector detects the carrier included in the signal in the training sequence. It assumes a logic "0" state, and the convergence operation of the tap gain of the equalizer AAE begins.

When the signal INITIAL is at logic "1", ie at the beginning of the training mode, according to the invention, selectors SEL0 and SEL1 are each switched to the side of contact 1. Therefore, in this state, signal B on lead 14 is 2
A signal level error signal representing the difference from the reference level REF1 is supplied by the attenuator SUB63 to the multiplier MLT51 of the loop filter 302 through the lead 306 and the selector SEL1. At this time, the selector SEL2 selects the larger loop gain α1 from the other input 212 of the multiplier MLT51.
is supplied. Therefore, as previously explained, the time constant of this loop filter 302 is now sufficiently small to allow the automatic gain control to quickly follow when the carrier wave first arrives at the input terminal 10 in the training sequence. Next, when a carrier wave detector (not shown) detects this carrier wave, the signal INITIAL becomes logic 0 after a predetermined time, so selectors SEL0 and SEL1
are respectively switched to the contact 0 side. Therefore, the multiplier MLT51 of the loop filter 302 inputs 3
08 is connected to the output 208 of the amplification factor error detector 200 via the selector SEL1, and the input 212 is connected to the smaller loop gain α0 via the selector SEL0. Therefore, the same operation as described for the embodiment of FIG. 4 is performed, controlling the amplification factor of the variable gain amplifier VGA based on the central tap gain C _p of the equalizer AAE.

Such gain adjustment typically spans a very large range, for example in a telephone line demodulator.
More than 40dB may be required. Therefore, it may be better to express the output level of the accumulator GAIN and the output A1 of the analog-to-digital converter ADC in a floating point format. The multiplier MLT66 is provided in the loop filter 302 of FIG. 5 in order to operate this automatic gain control loop under the same conditions regardless of the input signal level.

In the embodiments shown in FIGS. 4 and 5, the square of the absolute value of the central tap gain of the equalizer AAE |C _p | ² is used as the input of the subtractor SUB52 of the gain error detector 200. , instead of this |C _p |
may also be used, in which case the reference level given to the other input of the subtracter SUB52 is naturally
A value REF01 different from REF0 is used. In addition, in the automatic equalizer AAE, the carrier phase is controlled so that the imaginary part Im (C _p ) of the central tap gain becomes 0 and the real part Re (C _p ) becomes positive for carrier phase detection. In this case, the imaginary part of the central tap gain is the carrier phase error signal PE (Figure 1).
It can be used as In that case, the amplification factor error detector 200 of FIGS. 4 and 5 is a multiplier.
MLT53 and MLT54 and adder
ADD51 may be omitted. i.e. subtractor
The SUB 52 outputs a signal representing the difference between Re(Co) and REF01 to the lead 208 as an amplification factor error signal GE. Therefore, automatic gain control is performed so that Re(C _p )=REF01.

With this configuration, the automatic gain control circuit according to the present invention does not respond to changes in the average level of the input signal depending on the transmission symbol pattern, but only follows changes in line attenuation. .
Furthermore, in the training sequence of the demodulator, it does not respond to fluctuations in the average level of the input signal due to line characteristics when transitioning from binary symbol transmission to multi-level symbol transmission in data mode. Therefore, stable automatic gain control with a large time constant can be performed immediately after the training sequence ends, and a sufficiently low bit error rate can be achieved. Therefore, the present invention can be particularly effectively applied to modem modulators (MODEM) that require a very short effective training time.

A method in which the number of taps in the automatic equalizer is variable, that is, only the central tap and its neighboring taps are active at the beginning of the training sequence, reduces the delay of the automatic gain control loop, slightly improves the loop gain, and improves the timing. The automatic gain control circuit according to the present invention can be effectively combined with an automatic equalizer that reduces the constant, thereby achieving convergence in initial training, that is, automatic equalization, timing extraction, carrier detection, and automatic gain. Control is performed at high speed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of a receiving device including a demodulator to which an automatic gain control circuit according to the present invention is applied, FIG. 2 is a block diagram showing an example of a conventional automatic gain control circuit, and FIG. 3 is a block diagram showing an example of a conventional automatic gain control circuit. Functional diagrams showing the equivalent circuit paths of the loop filter shown in Figs. 4 and 5.
Each figure is a block diagram showing an embodiment of an automatic gain control circuit according to the present invention. Explanation of symbols of main parts, 200...Amplification factor error detector, 202, 302...Loop filter, 3
00...Signal level error detector, AAE...Automatic equalizer, AGC...Automatic gain control circuit, SEL1,
SEL2...Selector, VGA...Variable gain amplifier.

Claims (1)

[Claims] 1. Includes a variable gain amplifier and a loop filter that generates a gain control signal to control the gain of the variable gain amplifier, and supplies an automatically gain-controlled output signal to a demodulator having an automatic equalizer. an automatic gain control circuit comprising: a first error detection circuit that generates a first signal representative of a gain error of the variable gain amplifier based on a center tap gain of the automatic equalizer; An automatic gain control circuit characterized in that a filter supplies the gain control signal according to the first signal to the variable gain amplifier, thereby stabilizing the level of the output signal. 2. In an automatic gain control circuit that includes a variable gain amplifier and a loop filter that generates a gain control signal to control the gain of the variable gain amplifier, and supplies an automatically gain-controlled output signal to a demodulator having an automatic equalizer. , the circuit includes: a first error detection circuit that generates a first signal representative of the gain error of the variable gain amplifier based on the center tap gain of the automatic equalizer; and a first error detection circuit representative of the error in the level of the output signal. a second error detection circuit that generates a second signal; and a second error detection circuit that selectively takes the first and second states and changes the signal from the first state to the first state in response to a predetermined point in time during the training period of the automatic equalizer. switching means for transitioning to a second state; the switching means connects a second error detection circuit to the loop filter in the first state;
, and in a second state, a first error detection circuit is connected to the loop filter to supply the first signal to the loop filter, and the loop filter is connected to the second error detection circuit. An automatic gain control circuit characterized in that the gain control signal is supplied to the variable gain amplifier with a high loop gain depending on the first signal and with a low loop gain depending on the first signal.