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JPS6446798A - Display control system - Google Patents

Display control system

Info

Publication number
JPS6446798A
JPS6446798A JP62203443A JP20344387A JPS6446798A JP S6446798 A JPS6446798 A JP S6446798A JP 62203443 A JP62203443 A JP 62203443A JP 20344387 A JP20344387 A JP 20344387A JP S6446798 A JPS6446798 A JP S6446798A
Authority
JP
Japan
Prior art keywords
display
video data
video
control circuit
screens
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62203443A
Other languages
Japanese (ja)
Inventor
Hiroshi Wakabayashi
Yoshimichi Yahagi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62203443A priority Critical patent/JPS6446798A/en
Publication of JPS6446798A publication Critical patent/JPS6446798A/en
Pending legal-status Critical Current

Links

Landscapes

  • Controls And Circuits For Display Device (AREA)
  • Digital Computer Display Output (AREA)

Abstract

PURPOSE: To make it possible to display video data for two screens on one screen by reading out video data for two screens stored in a video memory with the timing of a display control circuit. CONSTITUTION: All of display timing is controlled by a display control circuit 11. A dual port memory 20 outputs video data for a 1st display screen to a data bus 4 by a display refresh access and the Video data are inputted to a video control circuit 7 as video data 6. On the other hand, a display refresh access for a 2nd display screen is read out by using a serial data bus 21 for the memory 20. Video data for the 2nd display screen are outputted to the bus 21, inputted to the circuit 7 as video data 24 and mixed with the video data 6. Consequently, a picture mutually superposing the 1st and 2nd display screens is displayed.
JP62203443A 1987-08-18 1987-08-18 Display control system Pending JPS6446798A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62203443A JPS6446798A (en) 1987-08-18 1987-08-18 Display control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62203443A JPS6446798A (en) 1987-08-18 1987-08-18 Display control system

Publications (1)

Publication Number Publication Date
JPS6446798A true JPS6446798A (en) 1989-02-21

Family

ID=16474194

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62203443A Pending JPS6446798A (en) 1987-08-18 1987-08-18 Display control system

Country Status (1)

Country Link
JP (1) JPS6446798A (en)

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