JPS6445399U - - Google Patents
Info
- Publication number
- JPS6445399U JPS6445399U JP14122487U JP14122487U JPS6445399U JP S6445399 U JPS6445399 U JP S6445399U JP 14122487 U JP14122487 U JP 14122487U JP 14122487 U JP14122487 U JP 14122487U JP S6445399 U JPS6445399 U JP S6445399U
- Authority
- JP
- Japan
- Prior art keywords
- connector
- input terminal
- output
- terminal
- connector means
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Description
第1図はこの考案のメモリ書込み用アダプタの
実施例を示す結線図、第2図は第1図のメモリ書
込み用アダプタを用いて構成したメモリ書込みシ
ステムのシステム構成図、第3図は第2図のメモ
リボード11の概略を示すブロツク図、第4図は
従来のメモリボードの概略を示すブロツク図であ
る。
FIG. 1 is a wiring diagram showing an embodiment of the memory writing adapter of this invention, FIG. 2 is a system configuration diagram of a memory writing system configured using the memory writing adapter of FIG. 1, and FIG. 4 is a block diagram schematically showing the memory board 11 shown in FIG. 4. FIG. 4 is a block diagram schematically showing a conventional memory board.
Claims (1)
接続されるべきコネクタ手段と、 上記アダプタ本体に接続され、書込み装置のI
Cソケツトと接合されるべきICコネクタと、 そのICコネクタに備えられた、アウトプツト
イネーブル入力端子、モード制御入力端子、チツ
プイネーブル入力端子、アドレス入力端子、デー
タ入力端子と、 上記コネクタ手段に備えられた、読出し書込み
切替端子、複数のアウトプツトイネーブル出力端
子、モード制御出力端子、複数のチツプイネーブ
ル出力端子、アドレス出力端子、データ出力端子
と、 上記コネクタ手段の読出し書込み切替端子に所
定レベルの書込み信号を出力する書込み信号発生
手段と、 上記ICコネクタのアウトプツトイネーブル入
力端子を上記コネクタ手段の複数のアウトプツト
イネーブル出力端子の1つに選択的に接続する第
1IC選択スイツチと、 上記ICコネクタのチツプイネーブル入力端子
を上記コネクタ手段の複数のチツプイネーブル出
力端子の1つに選択的に接続する第2IC選択ス
イツチと 上記ICコネクタのモード制御入力端子及び上
記コネクタ手段のモード制御出力端子間を接続す
るモード制御線と、 上記ICコネクタのアドレス入力端子及び上記
コネクタ手段のアドレス出力端子間を接続する書
込み用アドレスバスと、 上記ICコネクタのデータ入力端子及び上記コ
ネクタ手段のデータ出力端子間を接続する書込み
用データバスと、 を具備するメモリ書込み用アダプタ。[Claims for Utility Model Registration] An adapter body; Connector means connected to the adapter body and to be connected to the memory board;
An IC connector to be connected to the C socket; an output enable input terminal, a mode control input terminal, a chip enable input terminal, an address input terminal, and a data input terminal provided on the IC connector; In addition, a write signal at a predetermined level is applied to a read/write switching terminal, a plurality of output enable output terminals, a mode control output terminal, a plurality of chip enable output terminals, an address output terminal, a data output terminal, and a read/write switching terminal of the connector means. a first IC selection switch that selectively connects an output enable input terminal of the IC connector to one of a plurality of output enable output terminals of the connector means; a chip of the IC connector; a second IC selection switch for selectively connecting an enable input terminal to one of a plurality of chip enable output terminals of the connector means; and a mode control switch for connecting between a mode control input terminal of the IC connector and a mode control output terminal of the connector means; a control line; a write address bus that connects between the address input terminal of the IC connector and the address output terminal of the connector means; and a write address bus that connects the data input terminal of the IC connector and the data output terminal of the connector means. A memory writing adapter equipped with a data bus and.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14122487U JPS6445399U (en) | 1987-09-14 | 1987-09-14 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14122487U JPS6445399U (en) | 1987-09-14 | 1987-09-14 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6445399U true JPS6445399U (en) | 1989-03-20 |
Family
ID=31406108
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP14122487U Pending JPS6445399U (en) | 1987-09-14 | 1987-09-14 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6445399U (en) |
-
1987
- 1987-09-14 JP JP14122487U patent/JPS6445399U/ja active Pending
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