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JPS6445147A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS6445147A
JPS6445147A JP20215387A JP20215387A JPS6445147A JP S6445147 A JPS6445147 A JP S6445147A JP 20215387 A JP20215387 A JP 20215387A JP 20215387 A JP20215387 A JP 20215387A JP S6445147 A JPS6445147 A JP S6445147A
Authority
JP
Japan
Prior art keywords
layer
wiring
metal wiring
miniaturization
vapor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP20215387A
Other languages
Japanese (ja)
Inventor
Kazuo Koga
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP20215387A priority Critical patent/JPS6445147A/en
Publication of JPS6445147A publication Critical patent/JPS6445147A/en
Pending legal-status Critical Current

Links

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To contrive the miniaturization and the high integration of the title semiconductor device by a method wherein a wiring structure of at least two or more layers is formed, and a direct continuity exists between an upper wiring layer and a substrate without the intermediary of the lower wiring layer. CONSTITUTION:A gate electrode 107 is formed on a semiconductor substrate 103, and after an interlayer insulating film 104 has been formed using a vapor- growth method, an aperture 108 with which a first layer of metal wiring 101 and the gate electrode 107 will be conducted is provided. Then, the first layer of metal wiring 101 is formed, and after an interlayer insulating film 105 has been formed thereon using a vapor-growth method, an aperture part 109 through which a second metal wiring 102 and the semiconductor 103 sill be conducted is perforated, and after the second layer wiring 102 has been formed, an insulating protective film 106 is formed. As a result, the miniaturization and high degree of integration of the device can be achieved.
JP20215387A 1987-08-13 1987-08-13 Semiconductor device Pending JPS6445147A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20215387A JPS6445147A (en) 1987-08-13 1987-08-13 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20215387A JPS6445147A (en) 1987-08-13 1987-08-13 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS6445147A true JPS6445147A (en) 1989-02-17

Family

ID=16452840

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20215387A Pending JPS6445147A (en) 1987-08-13 1987-08-13 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS6445147A (en)

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