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JPS6444628A - Error correction system - Google Patents

Error correction system

Info

Publication number
JPS6444628A
JPS6444628A JP20209387A JP20209387A JPS6444628A JP S6444628 A JPS6444628 A JP S6444628A JP 20209387 A JP20209387 A JP 20209387A JP 20209387 A JP20209387 A JP 20209387A JP S6444628 A JPS6444628 A JP S6444628A
Authority
JP
Japan
Prior art keywords
information
error
transmission
bit
significant bit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP20209387A
Other languages
Japanese (ja)
Inventor
Noboru Iizuka
Yoshimasa Ohora
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP20209387A priority Critical patent/JPS6444628A/en
Publication of JPS6444628A publication Critical patent/JPS6444628A/en
Pending legal-status Critical Current

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  • Error Detection And Correction (AREA)

Abstract

PURPOSE:To reduce the redundancy of a transmission signal and to improve the transmission efficiency by using the characteristic of transmission error generated at the time of transmission with analog amplitude information and only applying an error correction code to a specific bit (the least significant bit) to correct the error of the whole of transmission information. CONSTITUTION:The least significant bit of n-bit message digital information is encoded to the error correction code by an error correction code coding means 11, and information is converted to analog amplitude information by an analog information converting means 12 and is transmitted. The reception signal level (analog amplitude information) is converted to at least (n+1)-bit digital information by a digital information converting means 13, and the least significant bit of high-order (n) bits is subjected to error detection by an error detecting means 14. The least significant bit of (n+1) bits is used as error information, and an error correction code decoding means 15 is subjected high- order n-bit digital information to + or -1 operation processing based on error information at the time of detecting error at the least significant bit of high-order (n) bits, thereby correcting error of transmission information.
JP20209387A 1987-08-13 1987-08-13 Error correction system Pending JPS6444628A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20209387A JPS6444628A (en) 1987-08-13 1987-08-13 Error correction system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20209387A JPS6444628A (en) 1987-08-13 1987-08-13 Error correction system

Publications (1)

Publication Number Publication Date
JPS6444628A true JPS6444628A (en) 1989-02-17

Family

ID=16451851

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20209387A Pending JPS6444628A (en) 1987-08-13 1987-08-13 Error correction system

Country Status (1)

Country Link
JP (1) JPS6444628A (en)

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