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JPS6441534A - Data reception system - Google Patents

Data reception system

Info

Publication number
JPS6441534A
JPS6441534A JP62198411A JP19841187A JPS6441534A JP S6441534 A JPS6441534 A JP S6441534A JP 62198411 A JP62198411 A JP 62198411A JP 19841187 A JP19841187 A JP 19841187A JP S6441534 A JPS6441534 A JP S6441534A
Authority
JP
Japan
Prior art keywords
data
error
reception
parallel data
received
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62198411A
Other languages
Japanese (ja)
Inventor
Keiji Sadai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP62198411A priority Critical patent/JPS6441534A/en
Publication of JPS6441534A publication Critical patent/JPS6441534A/en
Pending legal-status Critical Current

Links

Landscapes

  • Communication Control (AREA)
  • Computer And Data Communications (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)

Abstract

PURPOSE:To attain flexible processing in response to the content of an error by storing a received parallel data subject to serial parallel conversion with line fault and status information added thereto at the reception of each parallel data and identifying the data received in error based on the said information. CONSTITUTION:A reception means 1 converts a received bit serial data into a parallel data. A reception status detection means 2 detects the presence of the reception error for each parallel data and stores a data representing the presence of the detected reception error into a storage means 3 in correspondence to the parallel data. Thus, the data received in error among the parallel data is identified based on the parallel data stored in the storage means 3 and the data representing the presence of reception error. Thus, the parallel data received in error is identified based on the data and the data is processed in response to the content of error so as to allow to cope flexibly with the reception error.
JP62198411A 1987-08-07 1987-08-07 Data reception system Pending JPS6441534A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62198411A JPS6441534A (en) 1987-08-07 1987-08-07 Data reception system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62198411A JPS6441534A (en) 1987-08-07 1987-08-07 Data reception system

Publications (1)

Publication Number Publication Date
JPS6441534A true JPS6441534A (en) 1989-02-13

Family

ID=16390674

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62198411A Pending JPS6441534A (en) 1987-08-07 1987-08-07 Data reception system

Country Status (1)

Country Link
JP (1) JPS6441534A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5590152A (en) * 1978-12-27 1980-07-08 Toshiba Corp Error control system
JPS62159933A (en) * 1986-01-09 1987-07-15 Nec Corp Frame synchronizing detection circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5590152A (en) * 1978-12-27 1980-07-08 Toshiba Corp Error control system
JPS62159933A (en) * 1986-01-09 1987-07-15 Nec Corp Frame synchronizing detection circuit

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