JPS6437038A - Junction of semiconductor materials - Google Patents
Junction of semiconductor materialsInfo
- Publication number
- JPS6437038A JPS6437038A JP62193338A JP19333887A JPS6437038A JP S6437038 A JPS6437038 A JP S6437038A JP 62193338 A JP62193338 A JP 62193338A JP 19333887 A JP19333887 A JP 19333887A JP S6437038 A JPS6437038 A JP S6437038A
- Authority
- JP
- Japan
- Prior art keywords
- wire
- ball
- section
- sections
- semiconductor material
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000463 material Substances 0.000 title abstract 5
- 239000004065 semiconductor Substances 0.000 title abstract 5
- 239000000956 alloy Substances 0.000 abstract 2
- 229910045601 alloy Inorganic materials 0.000 abstract 2
- 230000015572 biosynthetic process Effects 0.000 abstract 2
- 238000000034 method Methods 0.000 abstract 2
- 230000000717 retained effect Effects 0.000 abstract 2
- 239000000758 substrate Substances 0.000 abstract 2
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
- H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
- H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/78—Apparatus for connecting with wire connectors
- H01L2224/7825—Means for applying energy, e.g. heating means
- H01L2224/783—Means for applying energy, e.g. heating means by means of pressure
- H01L2224/78301—Capillary
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
PURPOSE:To prevent a junction from peeling-off or cracks by a method wherein strain in presence between a substrate and a chip is effectively absorbed by a wire section retained on a ball in a process employing a wire bonder to deliver a bump electrode. CONSTITUTION:The end of a wire section 5a of an alloy wire 5 is heated for the formation of a ball section 7, the alloy wire 5 is pulled with the ball section 7 bonded to a semiconductor material 3, and the ball section 7 is delivered upward with the wire section 5a retained thereon. Similar ball sections 7 are provided in plurality, the top ends 5a' of wire sections 5a are disconnected to unify the length, ball sections 7' deliverd to the other part of the surface of the semiconductor material 3 are connected to the upper ends of the wire sections 5a for the formation of bump electrodes 7a and, through the intermediary of the bump electrode 7a, wirings 2 and the semiconductor material 3 are connected. In this design, the wire sections 5a absorbs stress attributable to the difference in thermal expansion coefficient between the substrate 1 and the semiconductor material 3, preventing a junction between the bump electrodes 7a and the wirings 2 or electrodes 3a from peeling-off or cracks.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62193338A JPS6437038A (en) | 1987-07-31 | 1987-07-31 | Junction of semiconductor materials |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62193338A JPS6437038A (en) | 1987-07-31 | 1987-07-31 | Junction of semiconductor materials |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6437038A true JPS6437038A (en) | 1989-02-07 |
JPH0533820B2 JPH0533820B2 (en) | 1993-05-20 |
Family
ID=16306232
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62193338A Granted JPS6437038A (en) | 1987-07-31 | 1987-07-31 | Junction of semiconductor materials |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6437038A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0394438A (en) * | 1989-09-06 | 1991-04-19 | Shinko Electric Ind Co Ltd | Semiconductor chip module |
JP2008091888A (en) * | 2006-09-22 | 2008-04-17 | Stats Chippac Inc | Fusible input / output interconnect system and method for flip chip packaging with stud bumps attached to a substrate |
US9847309B2 (en) | 2006-09-22 | 2017-12-19 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming vertical interconnect structure between semiconductor die and substrate |
-
1987
- 1987-07-31 JP JP62193338A patent/JPS6437038A/en active Granted
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0394438A (en) * | 1989-09-06 | 1991-04-19 | Shinko Electric Ind Co Ltd | Semiconductor chip module |
JP2008091888A (en) * | 2006-09-22 | 2008-04-17 | Stats Chippac Inc | Fusible input / output interconnect system and method for flip chip packaging with stud bumps attached to a substrate |
US9847309B2 (en) | 2006-09-22 | 2017-12-19 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming vertical interconnect structure between semiconductor die and substrate |
Also Published As
Publication number | Publication date |
---|---|
JPH0533820B2 (en) | 1993-05-20 |
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