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JPS6436351A - Disk cache system - Google Patents

Disk cache system

Info

Publication number
JPS6436351A
JPS6436351A JP62192188A JP19218887A JPS6436351A JP S6436351 A JPS6436351 A JP S6436351A JP 62192188 A JP62192188 A JP 62192188A JP 19218887 A JP19218887 A JP 19218887A JP S6436351 A JPS6436351 A JP S6436351A
Authority
JP
Japan
Prior art keywords
write
mode
data
change command
mode change
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62192188A
Other languages
Japanese (ja)
Inventor
Shinzo Masui
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Alps Alpine Co Ltd
Original Assignee
Alps Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alps Electric Co Ltd filed Critical Alps Electric Co Ltd
Priority to JP62192188A priority Critical patent/JPS6436351A/en
Publication of JPS6436351A publication Critical patent/JPS6436351A/en
Pending legal-status Critical Current

Links

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  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE:To employ only the advantages of two processing systems which guarantee high speed in disk access and the safety of data, by switching a mode to a write back system or a write through system by issuing a mode change command subsequently corresponding to the kind of the data. CONSTITUTION:The mode is switched to the write back system or the write through system by issuing the mode change command subsequently corresponding to the kind of the data. In other words, it is possible to switch a processing system at the time of writing to a desired mode, the write through system or the write back system, by sending a write mode change command from a host side. Thus, since it is possible to select an objective processing system of write by switching at every case by a user, the safety of important data can be guaranteed while securing the high speed of access.
JP62192188A 1987-07-31 1987-07-31 Disk cache system Pending JPS6436351A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62192188A JPS6436351A (en) 1987-07-31 1987-07-31 Disk cache system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62192188A JPS6436351A (en) 1987-07-31 1987-07-31 Disk cache system

Publications (1)

Publication Number Publication Date
JPS6436351A true JPS6436351A (en) 1989-02-07

Family

ID=16287142

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62192188A Pending JPS6436351A (en) 1987-07-31 1987-07-31 Disk cache system

Country Status (1)

Country Link
JP (1) JPS6436351A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03208145A (en) * 1990-01-10 1991-09-11 Matsushita Electric Ind Co Ltd Information recording and reproducing device
US5205582A (en) * 1990-09-20 1993-04-27 Honda Giken Kogyo Kabushiki Kaisha Occupant protective system
JPH05241954A (en) * 1991-10-11 1993-09-21 Intel Corp Processor
US5524234A (en) * 1992-11-13 1996-06-04 Cyrix Corporation Coherency for write-back cache in a system designed for write-through cache including write-back latency control
US5606681A (en) * 1994-03-02 1997-02-25 Eec Systems, Inc. Method and device implementing software virtual disk in computer RAM that uses a cache of IRPs to increase system performance
US6052789A (en) * 1994-03-02 2000-04-18 Packard Bell Nec, Inc. Power management architecture for a reconfigurable write-back cache
US6651136B2 (en) 1994-05-06 2003-11-18 Superspeed Software, Inc. Method and system for coherently caching I/O devices across a network

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60126750A (en) * 1983-12-14 1985-07-06 Hitachi Ltd cache memory device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60126750A (en) * 1983-12-14 1985-07-06 Hitachi Ltd cache memory device

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03208145A (en) * 1990-01-10 1991-09-11 Matsushita Electric Ind Co Ltd Information recording and reproducing device
US5205582A (en) * 1990-09-20 1993-04-27 Honda Giken Kogyo Kabushiki Kaisha Occupant protective system
JPH05241954A (en) * 1991-10-11 1993-09-21 Intel Corp Processor
US5524234A (en) * 1992-11-13 1996-06-04 Cyrix Corporation Coherency for write-back cache in a system designed for write-through cache including write-back latency control
US5606681A (en) * 1994-03-02 1997-02-25 Eec Systems, Inc. Method and device implementing software virtual disk in computer RAM that uses a cache of IRPs to increase system performance
US6052789A (en) * 1994-03-02 2000-04-18 Packard Bell Nec, Inc. Power management architecture for a reconfigurable write-back cache
US6651136B2 (en) 1994-05-06 2003-11-18 Superspeed Software, Inc. Method and system for coherently caching I/O devices across a network
US7017013B2 (en) 1994-05-06 2006-03-21 Superspeed Software, Inc. Method and system for coherently caching I/O devices across a network
US7039767B2 (en) 1994-05-06 2006-05-02 Superspeed Software, Inc. Method and system for coherently caching I/O devices across a network
US7111129B2 (en) 1994-05-06 2006-09-19 Superspeed Llc Method and system for coherently caching I/O devices across a network

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