JPS6434016A - Output driver circuit - Google Patents
Output driver circuitInfo
- Publication number
- JPS6434016A JPS6434016A JP62190829A JP19082987A JPS6434016A JP S6434016 A JPS6434016 A JP S6434016A JP 62190829 A JP62190829 A JP 62190829A JP 19082987 A JP19082987 A JP 19082987A JP S6434016 A JPS6434016 A JP S6434016A
- Authority
- JP
- Japan
- Prior art keywords
- state
- changes
- channel
- mos transistor
- channel mos
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 abstract 2
- 238000007599 discharging Methods 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00346—Modifications for eliminating interference or parasitic voltages or currents
- H03K19/00361—Modifications for eliminating interference or parasitic voltages or currents in field effect transistor circuits
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Electronic Switches (AREA)
- Logic Circuits (AREA)
Abstract
PURPOSE:To reduce a current noise, by providing a means which prevents a through current from being permitted to flow on a P-channel MOS transistor and an N-channel MOS transistor at the front stage of an output driver circuit, and suppressing the peak current of charging/discharging from a load capacitor. CONSTITUTION:When an input terminal I changes from (0) to (1), the output of a NOR gate 1 changes from (1) to (0), and the N-channel MOS transistor 1 changes from an ON state to an OFF state. Simultaneously, the N-channel transistor 2 changes from the ON state to the OFF state via an inverter 10 and a NOR gate 12, and simultaneously, the N-channel MOS transistor 3 changes from the ON state to the OFF state via a NOR gate 14. Therefore, no through current from the P-channel MOS transistor to the N-channel transistor is generated at all. Afterwards, the P-channel transistor 1 is set at the ON state, then, starts the charging to the load capacitor C. Thus, by turning ON three P-channel transistors 100, 200, and 300 keeping a certain time interval, a charging peak current can be suppressed, thereby, the current noise can be reduced.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62190829A JPS6434016A (en) | 1987-07-29 | 1987-07-29 | Output driver circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62190829A JPS6434016A (en) | 1987-07-29 | 1987-07-29 | Output driver circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6434016A true JPS6434016A (en) | 1989-02-03 |
Family
ID=16264454
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62190829A Pending JPS6434016A (en) | 1987-07-29 | 1987-07-29 | Output driver circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6434016A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6066958A (en) * | 1998-06-03 | 2000-05-23 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor integrated circuit |
| US6489815B2 (en) | 2000-04-26 | 2002-12-03 | Nec Corporation | Low-noise buffer circuit that suppresses current variation |
| KR100500927B1 (en) * | 1998-10-28 | 2005-10-24 | 주식회사 하이닉스반도체 | Output buffer of semiconductor device |
-
1987
- 1987-07-29 JP JP62190829A patent/JPS6434016A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6066958A (en) * | 1998-06-03 | 2000-05-23 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor integrated circuit |
| KR100500927B1 (en) * | 1998-10-28 | 2005-10-24 | 주식회사 하이닉스반도체 | Output buffer of semiconductor device |
| US6489815B2 (en) | 2000-04-26 | 2002-12-03 | Nec Corporation | Low-noise buffer circuit that suppresses current variation |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS6471217A (en) | Output buffer circuit | |
| JPS5746536A (en) | Gate circuit | |
| EP0332301A3 (en) | Time variant drive for use in integrated circuits | |
| JPS6437797A (en) | Eprom device | |
| IE813069L (en) | Buffer circuit | |
| US4894560A (en) | Dual-slope waveform generation circuit | |
| KR940027316A (en) | Integrated circuit with low power mode and clock amplifier circuit | |
| IE813068L (en) | Semiconductor buffer circuit | |
| KR910015114A (en) | Semiconductor digital circuits | |
| US4870609A (en) | High speed full adder using complementary input-output signals | |
| KR890005995A (en) | Bipolar-Complementary Metal Oxide Semiconductor Inverter | |
| JPS6468021A (en) | Logic circuit | |
| JPS6434016A (en) | Output driver circuit | |
| US5095229A (en) | Full-swing bicmos driver | |
| JPS5612128A (en) | Cmos buffer circuit | |
| JPH0318119A (en) | Complementary type metallic-oxide semiconductor translator | |
| JPS6473817A (en) | Input channel for mos ic | |
| GB1520078A (en) | Integrated mis driver stage | |
| US5289061A (en) | Output gate for a semiconductor IC | |
| KR940000252Y1 (en) | CMOS NANDGATE | |
| JPS6419417A (en) | Constant voltage source circuit | |
| JPS6454816A (en) | Cmos inverter circuit | |
| JPS6441924A (en) | Logic circuit | |
| JPS5713819A (en) | Output interface circuit | |
| JPS6416118A (en) | Gate driving circuit |