JPS6428787A - Memory device for pipe line type picture processor - Google Patents

Abstract

PURPOSE:To obtain a high speed picture memory device for a pipe line type picture processor at low cost by providing an address generating circuit, a logical circuit, a buffer circuit and a bus interface control circuit and executing a high speed access. CONSTITUTION:At the time of reading, the four picture elements, sum of respective one from memory chip modules 102-105 are read in parallel, rearranged in a logically correct sequence in the logic circuit 106 and temporarily stored in a buffer mechanism 107 in a sequence of a raster scanning. These data is sequentially read to a bus 110 by a control signal from an external bus 110 in the bus interface control circuit 108. At the time of writing, picture element data applied on an external bus 111 together with the control signal is temporarily stored in the mechanism 107 sequentially by the control of the circuit 108. These data is read according to a timing from the address generating circuit 101, the circuit 106 is rearranged correspondingly to the module to write the every collection of the four picture elements in parallel. The constitution of the circuits 101, 106 is changed, thereby, a reading and a writing from an arbitrary raster direction can be attained.