JPS6427092A - Output circuit - Google Patents
Output circuitInfo
- Publication number
- JPS6427092A JPS6427092A JP62183865A JP18386587A JPS6427092A JP S6427092 A JPS6427092 A JP S6427092A JP 62183865 A JP62183865 A JP 62183865A JP 18386587 A JP18386587 A JP 18386587A JP S6427092 A JPS6427092 A JP S6427092A
- Authority
- JP
- Japan
- Prior art keywords
- output
- time
- gate
- delay circuit
- charging
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000007599 discharging Methods 0.000 abstract 3
- LKKMLIBUAXYLOY-UHFFFAOYSA-N 3-Amino-1-methyl-5H-pyrido[4,3-b]indole Chemical compound N1C2=CC=CC=C2C2=C1C=C(N)N=C2C LKKMLIBUAXYLOY-UHFFFAOYSA-N 0.000 abstract 1
- 102100031413 L-dopachrome tautomerase Human genes 0.000 abstract 1
- 101710093778 L-dopachrome tautomerase Proteins 0.000 abstract 1
Landscapes
- Logic Circuits (AREA)
- Dram (AREA)
Abstract
PURPOSE:To decrease noise based on the sudden change of a charging and discharging current by minimizing influence to output characteristics and restricting the variation in time of the charging and discharging current and a maximum value at the time of the output change of an IC memory. CONSTITUTION:After an output data signal D, an output control signal OE and the inverse of OE are passed through a NOR gate 1 and a NAND gate 2 respectively, a signals O1 and O3 inverted at inverters 5 and 6 are inputted into the gates of transistor TRP1 and N3 respectively. Signals O2 and O4, which are obtained by passing the output signal of the NOR gate 1 and the NAND gate 2 through a leading delay circuit consisting of a delay circuit 3 and a NAND gate 7 and a trailing delay circuit consisting of a delay circuit 4 and a NOR gate 8, are inputted into the gates of TRP2 and N4 respectively. Thus, an output signal OUT and a current IC at the time of output charging and discharging go to a waveform shown by full lines in which the change in time and the maximum value of the current, compared with broken line characteristics when TRP1, P2, TRN3 and N4 turn on/off respective at the same time.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62183865A JPS6427092A (en) | 1987-07-22 | 1987-07-22 | Output circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62183865A JPS6427092A (en) | 1987-07-22 | 1987-07-22 | Output circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6427092A true JPS6427092A (en) | 1989-01-30 |
Family
ID=16143181
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62183865A Pending JPS6427092A (en) | 1987-07-22 | 1987-07-22 | Output circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6427092A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06196981A (en) * | 1991-07-16 | 1994-07-15 | Samsung Semiconductor Inc | Programmable output driver circuit and its realization |
| KR100511824B1 (en) * | 1997-06-27 | 2005-11-22 | 소니 일렉트로닉스 인코포레이티드 | Apparatus and method of providing a programmable slew rate control output driver |
-
1987
- 1987-07-22 JP JP62183865A patent/JPS6427092A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06196981A (en) * | 1991-07-16 | 1994-07-15 | Samsung Semiconductor Inc | Programmable output driver circuit and its realization |
| KR100511824B1 (en) * | 1997-06-27 | 2005-11-22 | 소니 일렉트로닉스 인코포레이티드 | Apparatus and method of providing a programmable slew rate control output driver |
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