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JPS6426949A - Transfer controller for memory data - Google Patents

Transfer controller for memory data

Info

Publication number
JPS6426949A
JPS6426949A JP18438087A JP18438087A JPS6426949A JP S6426949 A JPS6426949 A JP S6426949A JP 18438087 A JP18438087 A JP 18438087A JP 18438087 A JP18438087 A JP 18438087A JP S6426949 A JPS6426949 A JP S6426949A
Authority
JP
Japan
Prior art keywords
data
display area
written
address
register
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18438087A
Other languages
Japanese (ja)
Inventor
Tomio Henmi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujifilm Business Innovation Corp
Original Assignee
Fuji Xerox Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Xerox Co Ltd filed Critical Fuji Xerox Co Ltd
Priority to JP18438087A priority Critical patent/JPS6426949A/en
Publication of JPS6426949A publication Critical patent/JPS6426949A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To transfer a large quantity of data in a short time by using a means which writes the same data into plural areas in a memory just with a single transfer operation. CONSTITUTION:N is loaded into a writing frequency counting register 1, A0 set on a transfer width register 3 and the address initial value set to A respectively. Under such conditions, a command is delivered for transfer of the picture data D to a display area from a picture memory. The data D is written into the address A of the display area and therefore the value of the register 1 is subtracted by 1 down to N-1. Furthermore the same data D is written into the address A+A0 of the display area. Then the subtracted value of the register 1 is equal to N-2 and the data D is written into the address A+2A0 of the display area. Thus the same data D are written into the addresses A, A+A0, A+2A0... of the display area.
JP18438087A 1987-07-23 1987-07-23 Transfer controller for memory data Pending JPS6426949A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18438087A JPS6426949A (en) 1987-07-23 1987-07-23 Transfer controller for memory data

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18438087A JPS6426949A (en) 1987-07-23 1987-07-23 Transfer controller for memory data

Publications (1)

Publication Number Publication Date
JPS6426949A true JPS6426949A (en) 1989-01-30

Family

ID=16152181

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18438087A Pending JPS6426949A (en) 1987-07-23 1987-07-23 Transfer controller for memory data

Country Status (1)

Country Link
JP (1) JPS6426949A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59220855A (en) * 1983-05-31 1984-12-12 Toshiba Corp Memory access control system
JPS60123956A (en) * 1983-12-09 1985-07-02 Hitachi Ltd memory writing device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59220855A (en) * 1983-05-31 1984-12-12 Toshiba Corp Memory access control system
JPS60123956A (en) * 1983-12-09 1985-07-02 Hitachi Ltd memory writing device

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