JPS642484A - Clock synchronizing circuit of sampling rate converting circuit - Google Patents
Clock synchronizing circuit of sampling rate converting circuitInfo
- Publication number
- JPS642484A JPS642484A JP62158349A JP15834987A JPS642484A JP S642484 A JPS642484 A JP S642484A JP 62158349 A JP62158349 A JP 62158349A JP 15834987 A JP15834987 A JP 15834987A JP S642484 A JPS642484 A JP S642484A
- Authority
- JP
- Japan
- Prior art keywords
- variable oscillator
- circuit
- variable
- oscillation
- oscillation frequency
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000005070 sampling Methods 0.000 title abstract 3
- 230000010355 oscillation Effects 0.000 abstract 7
Landscapes
- Television Systems (AREA)
- Compression Or Coding Systems Of Tv Signals (AREA)
- Television Signal Processing For Recording (AREA)
Abstract
PURPOSE: To obtain 1st and 2nd clock signals of highly accurate frequency by supplying the output of a 1st phase-controlled variable oscillator and the output of a 2nd variable oscillator to a 2nd phase comparator for phase comparison and controlling the oscillation frequency of the 2nd variable oscillator.
CONSTITUTION: The 1st variable oscillator 5 which has an oscillation frequency equal to a 1st sampling frequency and the 2nd variable oscillator 12 which has the oscillation frequency equal to a 2nd sampling frequency are provided and the oscillation output of the variable oscillator 5 is compared by a 1st phase comparator 3 or 1 with the synchronizing signal of a 1st digital video signal to control the oscillation frequency of the 1st variable oscillator 5. Both oscillation outputs of variable oscillators 5 and 12 are compared by a 2nd phase comparator 10 to control the oscillation frequency of the 2nd variable oscillator 12, and the 1st and 2nd clock signals are obtained from the variable oscillators 5 and 12.
COPYRIGHT: (C)1989,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62158349A JP2508443B2 (en) | 1987-06-25 | 1987-06-25 | Clock synchronization circuit for sampling rate conversion circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62158349A JP2508443B2 (en) | 1987-06-25 | 1987-06-25 | Clock synchronization circuit for sampling rate conversion circuit |
Publications (3)
Publication Number | Publication Date |
---|---|
JPH012484A JPH012484A (en) | 1989-01-06 |
JPS642484A true JPS642484A (en) | 1989-01-06 |
JP2508443B2 JP2508443B2 (en) | 1996-06-19 |
Family
ID=15669705
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62158349A Expired - Fee Related JP2508443B2 (en) | 1987-06-25 | 1987-06-25 | Clock synchronization circuit for sampling rate conversion circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2508443B2 (en) |
-
1987
- 1987-06-25 JP JP62158349A patent/JP2508443B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JP2508443B2 (en) | 1996-06-19 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
LAPS | Cancellation because of no payment of annual fees |