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JPS6422060A - Solid-state image sensing device and its manufacture - Google Patents

Solid-state image sensing device and its manufacture

Info

Publication number
JPS6422060A
JPS6422060A JP62178412A JP17841287A JPS6422060A JP S6422060 A JPS6422060 A JP S6422060A JP 62178412 A JP62178412 A JP 62178412A JP 17841287 A JP17841287 A JP 17841287A JP S6422060 A JPS6422060 A JP S6422060A
Authority
JP
Japan
Prior art keywords
silicon
silicon layer
treating
gate insulating
vapor deposition
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62178412A
Other languages
Japanese (ja)
Inventor
Hideaki Oka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP62178412A priority Critical patent/JPS6422060A/en
Publication of JPS6422060A publication Critical patent/JPS6422060A/en
Pending legal-status Critical Current

Links

Landscapes

  • Solid State Image Pick-Up Elements (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)

Abstract

PURPOSE:To realize high resolution, high speed operation, and low voltage driving, by forming a silicon layer on a quartz substrate, polycrystallizing the silicon layer by heat-treating, and forming a gate insulating film. CONSTITUTION:Amorphous silicon, microcrystalline silicon etc., are made in the form of a film on a quartz substrate 101, by a method such as CVD method, plasma CVD method, vapor deposition method, EB vapor deposition method, MBE method and sputtering method. By heat-treating the above silicon layer 102 at 500-1200 deg.C, the amorphous silicon and the microcrystalline silicon are polycrystallized to form a polysrystalline silicon layer 102'. By thermal oxidizing method, a gate insulating film 103 is formed. Thereby, crystal grain diameter of the polycrystalline silicon can be grown up to 1mum or more. As the result, the mobility of electron can be made controllable in a wide range according to the crystal grain diameter, so that the high resolution and the high speed operation are faciliated.
JP62178412A 1987-07-17 1987-07-17 Solid-state image sensing device and its manufacture Pending JPS6422060A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62178412A JPS6422060A (en) 1987-07-17 1987-07-17 Solid-state image sensing device and its manufacture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62178412A JPS6422060A (en) 1987-07-17 1987-07-17 Solid-state image sensing device and its manufacture

Publications (1)

Publication Number Publication Date
JPS6422060A true JPS6422060A (en) 1989-01-25

Family

ID=16048042

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62178412A Pending JPS6422060A (en) 1987-07-17 1987-07-17 Solid-state image sensing device and its manufacture

Country Status (1)

Country Link
JP (1) JPS6422060A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6448577B1 (en) 1990-10-15 2002-09-10 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device with grain boundaries

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6448577B1 (en) 1990-10-15 2002-09-10 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device with grain boundaries

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