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JPS6421608A - Pc input/output signal processing system - Google Patents

Pc input/output signal processing system

Info

Publication number
JPS6421608A
JPS6421608A JP17857087A JP17857087A JPS6421608A JP S6421608 A JPS6421608 A JP S6421608A JP 17857087 A JP17857087 A JP 17857087A JP 17857087 A JP17857087 A JP 17857087A JP S6421608 A JPS6421608 A JP S6421608A
Authority
JP
Japan
Prior art keywords
signal
input
buffer
output
polarity
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP17857087A
Other languages
Japanese (ja)
Other versions
JP2616927B2 (en
Inventor
Nobuyuki Kitani
Yasushi Onishi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fanuc Corp
Original Assignee
Fanuc Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fanuc Corp filed Critical Fanuc Corp
Priority to JP62178570A priority Critical patent/JP2616927B2/en
Publication of JPS6421608A publication Critical patent/JPS6421608A/en
Application granted granted Critical
Publication of JP2616927B2 publication Critical patent/JP2616927B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Programmable Controllers (AREA)

Abstract

PURPOSE:To rewrite the polarity of logic easily by storing an input signal once into an input/output buffer and transferring it as it is or transferring it while the polarity is inverted depending on the conversion information thereby utilizing the rewrite of converting information. CONSTITUTION:A signal from an input circuit is stored as it is in an input buffer 31. As to the input conversion parameter 35, 0 is transferred as it is and the signal 1 is transferred while the polarity of the signal is inverted. Thus, signals of addresses DI0, DI1 are transferred while the polarity is inverted. Then the signal in the buffer 32 is processed by a control program 22 and written in an output image buffer 34. In the flow of the output signal, an output conversion parameter 36 corresponding to addresses DOB0-DOB3 of the buffer 34 is given and the signal is processed similarly as the input signal and transferred to the output buffer 33. The signal is outputted externally from the output circuit 3.
JP62178570A 1987-07-17 1987-07-17 Programmable controller Expired - Lifetime JP2616927B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62178570A JP2616927B2 (en) 1987-07-17 1987-07-17 Programmable controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62178570A JP2616927B2 (en) 1987-07-17 1987-07-17 Programmable controller

Publications (2)

Publication Number Publication Date
JPS6421608A true JPS6421608A (en) 1989-01-25
JP2616927B2 JP2616927B2 (en) 1997-06-04

Family

ID=16050790

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62178570A Expired - Lifetime JP2616927B2 (en) 1987-07-17 1987-07-17 Programmable controller

Country Status (1)

Country Link
JP (1) JP2616927B2 (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57193477U (en) * 1981-06-01 1982-12-08
JPS60193477U (en) * 1984-05-31 1985-12-23 日置電機株式会社 Trigger signal generator for logic signal observation equipment
JPS61173070U (en) * 1985-04-16 1986-10-28
JPS6345664A (en) * 1986-08-13 1988-02-26 Matsushita Electric Works Ltd I/o device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57193477U (en) * 1981-06-01 1982-12-08
JPS60193477U (en) * 1984-05-31 1985-12-23 日置電機株式会社 Trigger signal generator for logic signal observation equipment
JPS61173070U (en) * 1985-04-16 1986-10-28
JPS6345664A (en) * 1986-08-13 1988-02-26 Matsushita Electric Works Ltd I/o device

Also Published As

Publication number Publication date
JP2616927B2 (en) 1997-06-04

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