JPS641812B2 - - Google Patents

Description

[Detailed Description of the Invention] [Summary] Regarding the collection of history, which is the execution history of microprograms loaded into the control memory of a central processing unit and executed, a service processor is used to collect the history. Aiming at an economical control storage history method that requires a small amount of memory, the system is connected to a central processing unit that executes a microprogram stored in a control memory, and is connected to the central processing unit, and the microprogram is stored in the control memory. in a system having a processing device for loading
means for cyclically using a storage area of a history storage circuit to overwrite an address on the control memory storing the microprogram to be executed; and a means for overwriting the address to be stored and the contents of the comparison register. means for sending an interrupt signal to the processing unit when a match is made, and the central processing unit executes the microprogram loaded into the control memory with an error assigned by the processing unit, The processing device notifies the processing device of the existence of the control device corresponding to the address stored in the history storage circuit when receiving the notification and when receiving the interrupt signal due to the coincidence. If there is an error in each instruction on the control memory, the instruction is corrected and stored at the storage location of the address, and all the instructions on the control memory corresponding to the address stored in the history storage circuit are If there is no error in the instruction, one of the stored addresses other than the latest stored address is set in the comparison register.

[Industrial application field]

The present invention relates to collecting the history of a microprogram loaded into the control memory of a central processing unit and executed, and particularly to an economical control storage history method that requires a small amount of memory.

In a central processing unit that controls a microprogram, to check for logic errors in the microprogram or to investigate the cause of a failure, the microprogram is executed and a history consisting of the addresses of the executed microinstructions is recorded. It is collected as historical material.

[Problems to be solved by conventional technology and invention]

Conventionally, the history for the above purpose was created by executing a microprogram stored in a control memory (hereinafter referred to as CS) and sequentially storing the addresses on the CS of the executed microinstructions in a separately provided storage circuit. It was collected because of this.

In Japanese Patent Application No. 55-163019, the applicant of this application has forcibly loaded a microprogram with an error added to it in a central processing unit (hereinafter referred to as CPU) that stores microprograms in CS, and when executing the microprogram, proposed a method that uses the presence or absence of errors on the CS as a history by correcting errors in the read data.

Although this method eliminates the need for a storage circuit for storing the entire history and its control circuit as in the prior art, there are still relatively many circuits, etc. that need to be provided in the CPU for history collection.

The present invention aims at a control storage history method that can reduce the amount of memory and circuitry particularly required for history collection in a system having a so-called service processor (hereinafter referred to as SVP).

[Means for solving problems]

The figure is a block diagram showing the configuration of the present invention.

The figure shows the configuration related to history collection of the CPU and SVP, 1 is the SVP, 5 of the CPU is an output register that holds the instructions read from CS4, and 6 is the control that detects and corrects errors in the instructions in the output register 5. This is an error detection and correction circuit that outputs to the register 7 and also generates an interrupt signal to SVP1 when an error is detected.

Further, 8 of the CPU is a history detection unit that extracts an address from the instruction output from the error detection correction circuit 6 and stores it in the history storage circuit 9, and 10 is a history data register that holds the address read from the history storage circuit 9. 14 is a microprogram pointer register that specifies the storage address of the history storage circuit 9; 12 is a microprogram pointer register that specifies the storage address of the history storage circuit 9; and 12, the address set in the comparison register by SVP1 is compared with the address part of the instruction output from the error detection and correction circuit 6, and a match is found. This is an arithmetic unit that generates an interrupt signal to SVP1 when

[Effect]

When collecting the history of a microprogram, the SVP1 converts each instruction of the microprogram into a predetermined error detection and correction code, forcibly adds an error to it, loads it into the CS4, and starts execution of the CPU.

The CPU sequentially reads microprogram instructions determined by each machine instruction of the program to be executed from the CS 4 to the output register 5, detects and corrects errors in the error detection and correction circuit 6, and outputs them to the control register 7 as a correct microinstruction code. ,
Execution proceeds by generating control signals for each part of the CPU.

At the same time, the history detection section 8 extracts a predetermined portion indicating the address of the next microinstruction from the output of the error detection and correction circuit 6 and writes it into the history storage circuit 9.

At that time, the memory address of the history memory circuit 9 is cyclically designated by the microprogram pointer register (hereinafter referred to as MPT) 14, and thereby the memory address is overwritten in the history memory circuit 9. Ru.

In this way, execution of the machine instructions proceeds, and if an error is detected by the error detection and correction circuit 6 during this time, an interrupt signal is sent to the SVP 1 when the execution of the microprogram for one machine instruction is completed.

SVP1 then stops the CPU and reads CS4 using the address held in the history storage circuit 9. If there is an error in the read instruction, it corrects it and stores the correct instruction at the corresponding address of CS4. do.

If there are no errors in all the instructions read out from CS4 by SVP1 in this way, the history address in the storage area other than the last write address is loaded into comparison register 11, and CPU
Resumes execution.

The arithmetic unit 12 executes an error detection correction circuit 6 every time it reads and executes each instruction of the microprogram.
Compares the address part of the output with the contents of the comparison register 11, and if they match, it notifies SVP1 with an interrupt signal, and SVP1 also controls in this case in the same way as in the case of the interrupt signal due to an error. I do.

With the above method, even if the storage capacity of the history storage circuit 9 is extremely small regardless of the length of the microprogram, it is possible to trace the history of executed microprograms, and by sequentially modifying the microprogram portion, By reading the contents of CS4 at a required time, it is possible to identify whether the execution test has passed or not, depending on the presence or absence of errors.

〔Example〕

When collecting the history of a microprogram, the SVP1 converts each instruction of the microprogram into a predetermined error detection and correction code, forcibly adds an error to it, loads it into the CS4, and starts execution of the CPU.

As the error detection and correction code, for example, a known single error correction/double error detection (SECDED) code is used. In that case, SVP1 checks the correct instruction by error check code forming unit 2.
By forming a SECDED code and inverting one bit of each code through the error forming section 3, a correctable error is forcibly added to the CS4.
send to

In the CPU, the microprogram instruction counter (hereinafter referred to as MIC) 15
The instruction is read to the output register 5 from the address of the CS 4 specified by , the error detection and correction circuit 6 detects the error, corrects the correctable error, and outputs it to the control register 7 as a correct microinstruction. Execution proceeds by generating control signals for each part of the CPU.

The contents of the MIC 15 are determined by the address designation part of the microinstruction to be executed in a well-known manner, and are set for each microinstruction step via a control line via a circuit not shown.

At the same time, the history detection section 8 extracts the address specified in the address specification section of the microinstruction that is the output of the error detection correction circuit 6, and
Write to the history storage circuit 9. This address is also used for comparison by the arithmetic unit 12, which will be described later.

The write destination memory address of the history memory circuit 9 is specified by the MPT 14. Each time an address is written, the MPT 14 is advanced by +1 to indicate the next memory location, and the maximum address of the history memory circuit 9 is When it advances to 0, it returns to 0. In this way, the history storage circuit 9 is overwritten using the entire storage area cyclically.

If the microprogram is executed as described above and the error detection and correction circuit 6 detects an error, for example, when the microprogram execution for one machine instruction is finished,
An interrupt signal is generated to notify the detection of an abnormality in the CPU, and the interrupt signal is sent to SVP1.

During normal operation, the SVP1 records and diagnoses CPU failures, etc., but in the case of history collection, the SVP1 stops the CPU and controls the MPT14 to read the addresses held in the history storage circuit 9. The commands are sequentially read into the history data register 10, and each instruction of CS4 is sequentially read using the register.

If there is an error in the read instruction, the error correction unit 13 corrects the error and stores the correct instruction in the corresponding register of the CS4.

Also, if there are no errors in all the instructions read by SVP1 from CS4 in this way, it means that the microprogram in that part has already been executed and has been modified as described above. The occurrence of an interrupt indicates that an error occurred in the instruction at the address that was erased by overwriting.

Therefore, SVP1, for example, uses MPT14 when an interrupt occurs.
The address pointed to (which is the storage location to which the next history address is to be written, and corresponds to the storage location written at the earliest point in time on the history storage circuit 9) is loaded into the comparison register 11.

After any of the above processes, SVP1 resumes execution of the CPU.

When an address is set in the comparison register 11, the arithmetic unit 12 reads out and executes each instruction of the microprogram, and reads the address specifying part of the output of the error detection correction circuit 6 and the comparison register 11.
Compare the contents of , and if they match, SVP1
is notified by an interrupt signal.

Therefore, SVP1 is either address match or CS
An interrupt signal is received due to an error added to the instruction No. 4, and in either case, control is performed in the same manner as described above for the case of an interrupt signal due to an error.

When an interrupt occurs due to an address match, the address of the instruction with the error as described above is either the history part containing the address erased by overwriting from the history storage circuit 9, or it is closer to the address than in the previous case. A portion of the history that has been changed remains in the history storage circuit 9. Therefore, read CS4 with the address obtained in that case, correct any errors, and if all instructions are error-free again, store the oldest address in that case in the same way as above in the comparison register. Reset to 11.

In this way, the addresses set in the comparison register 11 can be sequentially traced back, and even if the microprogram of one machine instruction is long and the number of addresses in the history exceeds the storage capacity of the history storage circuit 9, the same machine By repeatedly executing the instructions, the instructions at those addresses on the CS4 can be successively modified.

With the above method, it is possible to track the history of executed microprograms even if the storage capacity of the history storage circuit 9 is extremely small regardless of the length of the microprogram.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, the history, which is the execution history of the microprogram loaded into the control memory of the central processing unit and executed, can be collected economically by using the service processor. There is a significant industrial effect in that it can be carried out.

[Brief explanation of the drawing]

The figure is a block diagram showing the configuration of the present invention. In the figure, 1 is SVP, 2 is error check code forming part, 3 is error forming part, 4 is CS, 5 is
is an output register, 6 is an error detection correction circuit, 7 is a control register, 8 is a history detection section, 9 is a history storage circuit, 10 is a history data register, 1
1 is a comparison register, 12 is an arithmetic unit, 13 is an error correction section, and 14 is an MPT.

Claims (1)

[Claims] 1. A system comprising a central processing unit that executes a microprogram stored in a control memory 4, and a processing unit 1 that is connected to the central processing unit and loads the microprogram into the control memory. means 8, 14 for overwriting the address on the control memory 4 storing the microprogram to be executed by cyclically using the storage area of the history storage circuit 9; and the address to be stored. Means 12 is provided for sending an interrupt signal to the processing device 1 when the contents of the comparison register 11 match, and the central processing device gives an error from the processing device 1 to the control memory 4. executes the microprogram loaded on the microprogram to notify the processing device of the existence of the error, and the processing device 1 executes the history when receiving the notification and when receiving the interrupt signal due to the coincidence. If there is an error in each instruction on the control memory 4 that corresponds to the address stored in the storage circuit 9, the instruction is corrected and stored at the storage location of the address, and the instruction is stored in the history storage circuit 9. If there is no error in all the instructions on the control memory 4 that correspond to the stored address, one of the stored addresses other than the latest stored address is transferred to the comparison register. 11. A control storage history method characterized in that the control storage history method is configured to be set to 11.