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JPS6417128A - Dynamic arrangement system for domain area of virtual computer - Google Patents

Dynamic arrangement system for domain area of virtual computer

Info

Publication number
JPS6417128A
JPS6417128A JP62172323A JP17232387A JPS6417128A JP S6417128 A JPS6417128 A JP S6417128A JP 62172323 A JP62172323 A JP 62172323A JP 17232387 A JP17232387 A JP 17232387A JP S6417128 A JPS6417128 A JP S6417128A
Authority
JP
Japan
Prior art keywords
area
memory
value
virtual computer
main memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62172323A
Other languages
Japanese (ja)
Inventor
Yukiyoshi Omura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP62172323A priority Critical patent/JPS6417128A/en
Publication of JPS6417128A publication Critical patent/JPS6417128A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)

Abstract

PURPOSE:To realize the continuation of the processing of a virtual computer which so far used an area including a memory error, by rearranging the information stored said area including the memory area into an idle area of a relevant memory. CONSTITUTION:When an error occurs in an area 31 of a main memory working in an operating system OS1, the operations of a CPU and an input/output device 8 which are used by the OS1 are stopped by a control program CP. Then the contents of the OS1 stored in the area 31 are moved to an idle area 4. Furthermore the registers (ABR and ALR) holding the value to check the propriety of the address value of the main memory when an access is given to this memory and a register (AMR) holding the value to check the propriety of the address value when a channel gives an access to the main memory are converted into the address values of the area 4. Then the OS1 is restored to its normal operation.
JP62172323A 1987-07-10 1987-07-10 Dynamic arrangement system for domain area of virtual computer Pending JPS6417128A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62172323A JPS6417128A (en) 1987-07-10 1987-07-10 Dynamic arrangement system for domain area of virtual computer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62172323A JPS6417128A (en) 1987-07-10 1987-07-10 Dynamic arrangement system for domain area of virtual computer

Publications (1)

Publication Number Publication Date
JPS6417128A true JPS6417128A (en) 1989-01-20

Family

ID=15939779

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62172323A Pending JPS6417128A (en) 1987-07-10 1987-07-10 Dynamic arrangement system for domain area of virtual computer

Country Status (1)

Country Link
JP (1) JPS6417128A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5369750A (en) * 1990-08-15 1994-11-29 Hitachi, Ltd. Method and apparatus for configuring multiple absolute address spaces
US6170039B1 (en) 1997-05-16 2001-01-02 Nec Corporation Memory controller for interchanging memory against memory error in interleave memory system
JPWO2013080288A1 (en) * 2011-11-28 2015-04-27 富士通株式会社 Memory degeneration method and information processing apparatus

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5888900A (en) * 1981-11-10 1983-05-27 インタ−ナシヨナル　ビジネス　マシ−ンズ　コ−ポレ−シヨン Memory element off-line system
JPS5990294A (en) * 1982-11-12 1984-05-24 Fujitsu Ltd Fixed area replacement method
JPS61195444A (en) * 1985-02-26 1986-08-29 Toshiba Corp Computer system

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5888900A (en) * 1981-11-10 1983-05-27 インタ−ナシヨナル　ビジネス　マシ−ンズ　コ−ポレ−シヨン Memory element off-line system
JPS5990294A (en) * 1982-11-12 1984-05-24 Fujitsu Ltd Fixed area replacement method
JPS61195444A (en) * 1985-02-26 1986-08-29 Toshiba Corp Computer system

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5369750A (en) * 1990-08-15 1994-11-29 Hitachi, Ltd. Method and apparatus for configuring multiple absolute address spaces
US6170039B1 (en) 1997-05-16 2001-01-02 Nec Corporation Memory controller for interchanging memory against memory error in interleave memory system
JPWO2013080288A1 (en) * 2011-11-28 2015-04-27 富士通株式会社 Memory degeneration method and information processing apparatus

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