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JPS6415948A - Semiconductor integtated circuit - Google Patents

Semiconductor integtated circuit

Info

Publication number
JPS6415948A
JPS6415948A JP62171981A JP17198187A JPS6415948A JP S6415948 A JPS6415948 A JP S6415948A JP 62171981 A JP62171981 A JP 62171981A JP 17198187 A JP17198187 A JP 17198187A JP S6415948 A JPS6415948 A JP S6415948A
Authority
JP
Japan
Prior art keywords
power supply
ground
wiring pattern
pad
split cell
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62171981A
Other languages
Japanese (ja)
Inventor
Takao Hirose
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62171981A priority Critical patent/JPS6415948A/en
Publication of JPS6415948A publication Critical patent/JPS6415948A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/10—Integrated device layouts

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Dram (AREA)

Abstract

PURPOSE:To reduce the occurrence of a noise due to the effect between cells and to prevent the malfunction by providing, for each split cell region, a power supply wiring pattern and a ground wiring pattern which are respectively connected to independent power supply and ground pads, thereby eliminating the effect between cells. CONSTITUTION:To a first split cell region 1, a power supply and a ground voltage are supplied through a power wiring pattern 6 from a power supply pad 4 and a ground wiring pattern 7 from a ground pad 5. Also, to a second split cell region 2, a power supply and a ground voltage are supplied through a power wiring pattern 16 from a power supply pad 8 and a ground wiring pattern 17 from a ground pad 9. Further, the respective power supply pads 4, 8 and ground pads 5, 9 of an input/output terminal region 3 are separately connected to external power supply lines. Therefore, the two split cell regions 1 and 2 can obtain power supplies which are independent from each other, whereby the number of concurrent operations of the circuit can be increased.
JP62171981A 1987-07-09 1987-07-09 Semiconductor integtated circuit Pending JPS6415948A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62171981A JPS6415948A (en) 1987-07-09 1987-07-09 Semiconductor integtated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62171981A JPS6415948A (en) 1987-07-09 1987-07-09 Semiconductor integtated circuit

Publications (1)

Publication Number Publication Date
JPS6415948A true JPS6415948A (en) 1989-01-19

Family

ID=15933322

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62171981A Pending JPS6415948A (en) 1987-07-09 1987-07-09 Semiconductor integtated circuit

Country Status (1)

Country Link
JP (1) JPS6415948A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5293334A (en) * 1990-11-30 1994-03-08 Kabushiki Kaisha Tobshiba Pattern layout of power source lines in semiconductor memory device
JP2020046225A (en) * 2018-09-14 2020-03-26 横河電機株式会社 Current input circuit and electric power measurer
JP2021517737A (en) * 2018-03-13 2021-07-26 キオクシア株式会社 Power Island Segmentation for Selective Bond Out

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5293334A (en) * 1990-11-30 1994-03-08 Kabushiki Kaisha Tobshiba Pattern layout of power source lines in semiconductor memory device
JP2021517737A (en) * 2018-03-13 2021-07-26 キオクシア株式会社 Power Island Segmentation for Selective Bond Out
JP2020046225A (en) * 2018-09-14 2020-03-26 横河電機株式会社 Current input circuit and electric power measurer

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