JPS6415855A - Data bus control system - Google Patents
Data bus control systemInfo
- Publication number
- JPS6415855A JPS6415855A JP17195087A JP17195087A JPS6415855A JP S6415855 A JPS6415855 A JP S6415855A JP 17195087 A JP17195087 A JP 17195087A JP 17195087 A JP17195087 A JP 17195087A JP S6415855 A JPS6415855 A JP S6415855A
- Authority
- JP
- Japan
- Prior art keywords
- data
- bus
- buffer
- control part
- data bus
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Bus Control (AREA)
Abstract
PURPOSE:To optimize the occupied time of a data bus and to smoothly process data by controlling the occupation and the release of the data bus via a control part in response to the quantity of the stored FIFO buffer data and the quantity of the transferred remaining data of a data bus control system. CONSTITUTION:A control part 4 of a data bus control system stores the input data into an FIFO buffer 1 and acquires the occupying right of a data bus 3 to a host device 2b to transfer data to the bus 3 from the buffer 1. Then the part 4 controls the occupation and the release of the bus 3 in response to the quantity of the acquired data and the quantity of the transferred remaining data of the buffer 1. Then a host I/F control part 40, an MPU 43, a data transfer control part 41, a ROM 44, a RAM 45, etc., are set to the part 4. The bus 3 is occupied when the quantity of data stored in the buffer 1 reaches a prescribed level and then released when the time needed for reading the quantity of the transferred remaining data exceeds a fixed level in an idle state of the buffer 1. Thus the occupied time of the bus 3 is optimized.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17195087A JPS6415855A (en) | 1987-07-09 | 1987-07-09 | Data bus control system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17195087A JPS6415855A (en) | 1987-07-09 | 1987-07-09 | Data bus control system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6415855A true JPS6415855A (en) | 1989-01-19 |
Family
ID=15932793
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP17195087A Pending JPS6415855A (en) | 1987-07-09 | 1987-07-09 | Data bus control system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6415855A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06175971A (en) * | 1992-09-17 | 1994-06-24 | Internatl Business Mach Corp <Ibm> | Personal computer system |
-
1987
- 1987-07-09 JP JP17195087A patent/JPS6415855A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06175971A (en) * | 1992-09-17 | 1994-06-24 | Internatl Business Mach Corp <Ibm> | Personal computer system |
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