JPS6412300U

JPS6412300U -

Info

Publication number: JPS6412300U
Application number: JP10375987U
Authority: JP
Priority date: 1987-07-06
Filing date: 1987-07-06
Publication date: 1989-01-23

Description

[Brief explanation of the drawing]

第１図は本考案のスタテイツクＲＡＭの一実施
例を示すブロツク図、第２図は従来例を示すブロ
ツク図である。１１……メモリマトリツクス、１２……入力系
、１３……出力系、１４……ライトアンプ、１５
，１９……カラムセレクタ、１６，２０……ロー
デコーダ、１７，２１……カラムデコーダ、１８
……アドレスレジスタ、２２……センスアンプ。 FIG. 1 is a block diagram showing one embodiment of the static RAM of the present invention, and FIG. 2 is a block diagram showing a conventional example. 11...Memory matrix, 12...Input system, 13...Output system, 14...Write amplifier, 15
, 19... Column selector, 16, 20... Row decoder, 17, 21... Column decoder, 18
...Address register, 22...Sense amplifier.

Claims

[Claims for Utility Model Registration] 1. A memory matrix for storing data, an input system for inputting data into this memory matrix in units of n bits, and a system for inputting data stored in the memory matrix in units of n×m bits ( (where m is an integer of 2 or more). 2. The input system includes a column selector that inputs n bits of data into the memory matrix at once, a row decoder that commands the number of columns of each data processed by this column selector, and a column decoder that commands the number of rows of each data. The output system includes a row decoder that commands the number of columns of each n×m bit data to be output, a column decoder that commands the number of rows of each data, and a The static RAM according to claim 1, further comprising a column selector that outputs n×m bits of data from a memory matrix at once.