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JPS6411346A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS6411346A
JPS6411346A JP16720687A JP16720687A JPS6411346A JP S6411346 A JPS6411346 A JP S6411346A JP 16720687 A JP16720687 A JP 16720687A JP 16720687 A JP16720687 A JP 16720687A JP S6411346 A JPS6411346 A JP S6411346A
Authority
JP
Japan
Prior art keywords
insulating film
hole
polysi
opened
interconnection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16720687A
Other languages
Japanese (ja)
Inventor
Shoichi Tanimura
Kosaku Yano
Hiroshi Nishimura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP16720687A priority Critical patent/JPS6411346A/en
Publication of JPS6411346A publication Critical patent/JPS6411346A/en
Pending legal-status Critical Current

Links

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To prevent faulty electrical connection between upper and lower layers of an insulating film as well as the etching development of the base surface at the bottom part of a hole by forming an electric conductor at a part wherein electrical connection is performed before completing the formation of the insulating film. CONSTITUTION:A thin insulating film is formed on a substrate wherein a Si substrate 1, a lower layer oxide film 2, a gate oxide film 3, the first layer interconnection 4 and so forth are formed and a hole is opened at a required place of the insulating film 5. Then, electric isolation between an electric conductor to be formed next and the first layer interconnection 4 and the like takes place and no failure of them develops. Among places wherein the hole is opened at the base insulating film 5, polySi 6 is formed at a place wherein its height is low and it makes the final hole 9 deep. After forming insulating films 7 on polySi 6, the hole 9 for use in connection is opened and an upper interconnection 8 is formed. The depth of the hole 9 becomes shallow and its state makes connection with the upper interconnection 8 sure and even if the Si surface is scraped, no problems such as fluctuations in the surface concentration of impurities and the like arise. Further, when a film wherein the thickness of an upper part of its insulating film varies according to the base form is used as the insulating films 7, the thickness of the insulating film is easily controlled by forming polySi 6 which is extruded at a lower part of substrate surface.
JP16720687A 1987-07-03 1987-07-03 Manufacture of semiconductor device Pending JPS6411346A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16720687A JPS6411346A (en) 1987-07-03 1987-07-03 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16720687A JPS6411346A (en) 1987-07-03 1987-07-03 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS6411346A true JPS6411346A (en) 1989-01-13

Family

ID=15845390

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16720687A Pending JPS6411346A (en) 1987-07-03 1987-07-03 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS6411346A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4933297A (en) * 1989-10-12 1990-06-12 At&T Bell Laboratories Method for etching windows having different depths
US4987099A (en) * 1989-12-29 1991-01-22 North American Philips Corp. Method for selectively filling contacts or vias or various depths with CVD tungsten

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60202954A (en) * 1984-03-27 1985-10-14 Mitsubishi Electric Corp Manufacture of semiconductor device
JPS61239646A (en) * 1985-04-16 1986-10-24 Nec Corp Formation of multilayer interconnection
JPS62118539A (en) * 1985-11-19 1987-05-29 Oki Electric Ind Co Ltd Formation of multilayer interconnection

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60202954A (en) * 1984-03-27 1985-10-14 Mitsubishi Electric Corp Manufacture of semiconductor device
JPS61239646A (en) * 1985-04-16 1986-10-24 Nec Corp Formation of multilayer interconnection
JPS62118539A (en) * 1985-11-19 1987-05-29 Oki Electric Ind Co Ltd Formation of multilayer interconnection

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4933297A (en) * 1989-10-12 1990-06-12 At&T Bell Laboratories Method for etching windows having different depths
US4987099A (en) * 1989-12-29 1991-01-22 North American Philips Corp. Method for selectively filling contacts or vias or various depths with CVD tungsten

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