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JPS6411345A - Formation of contact between interconnections - Google Patents

Formation of contact between interconnections

Info

Publication number
JPS6411345A
JPS6411345A JP16719187A JP16719187A JPS6411345A JP S6411345 A JPS6411345 A JP S6411345A JP 16719187 A JP16719187 A JP 16719187A JP 16719187 A JP16719187 A JP 16719187A JP S6411345 A JPS6411345 A JP S6411345A
Authority
JP
Japan
Prior art keywords
film
interconnection
contact
hole
interconnections
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16719187A
Other languages
Japanese (ja)
Inventor
Hiroshi Imai
Masabumi Kubota
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP16719187A priority Critical patent/JPS6411345A/en
Publication of JPS6411345A publication Critical patent/JPS6411345A/en
Pending legal-status Critical Current

Links

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To suppress contact resistance between the first and second interconnections so that it becomes sufficiently small by removing the surface of the first conductor interconnection up to a prescribed depth after performing a process wherein a through hole is formed and then, by forming thin films for use in the second conductor interconnection in multilayer interconnections. CONSTITUTION:In a state where a semiconductor substrate 1, a SiO2 film A2, the first Al interconnection 3, a SiO2 film B4, a photoresist film 5, a through hole 6, and a high resistance layer 7 are formed, reactive ion etching is carried out with a SiCl4 gas. Its treatment is performed on condition that an Al film of only about 0.1mum is etched. In this way, a part of about 0.1mum thick at the surface of a contact part of the first Al interconnection 3 is removed. (it is shown as an Al removal part 8). Then an aluminum metallic film is deposited in the same way that found conventionally and the second Al film 9 is formed. Thus, the high resistance layer 7 which has been formed at the surface of the contact part of the first Al interconnection 3 is removed together with the Al removal part 8 and the first Al interconnection 3 is connected with the second part Al film 9 at the part of the through hole 6 and then contact resistance between the above two parts can be suppressed so that it may become sufficiently small without exception.
JP16719187A 1987-07-03 1987-07-03 Formation of contact between interconnections Pending JPS6411345A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16719187A JPS6411345A (en) 1987-07-03 1987-07-03 Formation of contact between interconnections

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16719187A JPS6411345A (en) 1987-07-03 1987-07-03 Formation of contact between interconnections

Publications (1)

Publication Number Publication Date
JPS6411345A true JPS6411345A (en) 1989-01-13

Family

ID=15845118

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16719187A Pending JPS6411345A (en) 1987-07-03 1987-07-03 Formation of contact between interconnections

Country Status (1)

Country Link
JP (1) JPS6411345A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07183378A (en) * 1993-12-24 1995-07-21 Nec Corp Multilayer wiring structure and fabrication thereof
EP0691678A3 (en) * 1994-07-08 1997-10-01 Applied Materials Inc Method of etching contact holes in a dielectric layer by plasma, with removal of residues

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07183378A (en) * 1993-12-24 1995-07-21 Nec Corp Multilayer wiring structure and fabrication thereof
EP0691678A3 (en) * 1994-07-08 1997-10-01 Applied Materials Inc Method of etching contact holes in a dielectric layer by plasma, with removal of residues

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