JPS641056B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a multilayer wiring structure in a semiconductor device, particularly in a semiconductor integrated circuit device.

The need for multilayer wiring is increasing due to the increasing density of semiconductor integrated circuits, and various structures have been proposed, but problems remain with each method, and the reality is that there is no definitive solution. It is. In particular, prevention of short circuit between the lower electrode wiring layer and the upper electrode wiring layer,
It was insufficient to reduce the electrical resistance at the connection between these and to improve the adhesion between the upper electrode wiring layer and the interlayer insulating layer.

An object of the present invention is to provide a method for preventing short circuits, reducing electrical resistance at a connection portion, and improving adhesion.

The method according to the present invention uses an organic resin as an interlayer insulating film, and after coating this insulating film,
The method is characterized by etching the surface of the insulating film and the exposed parts of the lower wiring layer using mixed gas plasma of SF ₆ and O ₂ , and then forming the upper wiring layer. Hereinafter, the present invention will be explained in detail in comparison with the prior art.

An example of an interlayer insulating film that has been commonly used in the past is plasma nitride, which can be grown at a low temperature of 300 to 400°C. For example, in FIG. 1, a first aluminum electrode wiring layer 2 is formed on the surface of a silicon substrate 1 on which a diffusion process has been completed, and then a plasma nitride film 3 is grown. Next, photoetching is performed using CF ₄ gas plasma to form an opening 4 in the plasma nitride film 3 for interlayer connection, and then a second aluminum electrode wiring layer 5 is formed. After that, a polyimide film 6 for surface protection was applied.
is applied, and an opening 7 for wire bonding is formed by photoetching with hydrazine or the like.

The problem with this method is that the plasma nitride film 3
Since it is a vapor-phase grown film, pinholes are extremely likely to occur due to dust, etc., and the step coverage of the next layer (for example, the plasma nitride film 3 on the end surface 8 of the first aluminum electrode wiring layer 2) on the end surface of each layer is poor. In addition, there are many short-circuit accidents with the second aluminum electrode wiring layer 5 due to hillocks 9 that occur on the surface of the first aluminum electrode wiring layer 2, which is subjected to overlapping heat treatment processes.
The plasma nitride film 3 is not flexible, has a large difference in coefficient of thermal expansion from the aluminum layers 2 and 5, and is easily cracked. Therefore,
Normally, the film thickness of the first aluminum electrode wiring layer 2 is kept to 0.5 μm or less, and as a result, this structure has a severely limited rated current and is only applied to low-power integrated circuits. do not have.

FIG. 2 shows an embodiment of the invention. That is,
After the first aluminum electrode wiring layer 2 is formed on the surface of the silicon substrate 1 on which the diffusion process has been completed, a polyimide layer 10 is applied, and photoetching is performed using hydrazine to form openings 4 for interlayer connections. form.

After this, light dry etching is performed in SF ₆ (sulfur hexafluoride) and O ₂ (oxygen) gas plasma, and immediately a second aluminum layer 5 is formed by vapor deposition or magnetron sputtering. and perform photo-etching. This plasma treatment removes organic substances that have been decomposed or evaporated and redeposited from the surface of the polyimide layer 10, and at the same time,
Opening 4 in the first aluminum electrode wiring layer 2
It has the effect of etching and removing oxides such as alumina that occur on the surface of. This effect reduces the contact resistance between the first aluminum electrode wiring layer 2 and the second aluminum electrode wiring layer 5, and also reduces the contact resistance between the polyimide layer 10, which is an interlayer insulating film, and the second aluminum electrode wiring layer. The mechanical adhesion strength with layer 5 could be improved. It is also possible to provide the second layer aluminum electrode 5 with a connection portion to an external circuit that requires particularly high adhesion strength, and the degree of freedom in pattern design is increased. Thereafter, a surface protective polyimide film 6 is formed, and an opening 7 for wire bonding is formed therein.

In the semiconductor integrated circuit made in this way, since the polyimide layer 10, which is an interlayer insulating film, is relatively thick at 2.0 μm, the first aluminum electrode wiring layer 2
Even the hillock 9 generated during the process will not cause a short circuit with the second aluminum electrode wiring layer 5.
Moreover, the film thickness of the first aluminum electrode wiring layer 2 can be made relatively thick at 1.0 to 1.7 μm.
It has become possible to apply this method to medium-power integrated circuits with relatively high current densities. Furthermore, polyimide has lower costs for layer formation and processing than plasma nitride films, and is suitable for mass-produced products such as semiconductor integrated circuits for consumer use.

The scope of application of the present invention is not limited to the two-layer wiring structure shown in one embodiment, but can also be applied to multilayer wiring of three or more layers. It is clear that the interlayer insulating film is not limited to polyimide and can be applied to all polymers. Further, in addition to aluminum mentioned as the electrode metal, it is also applicable to single metals such as molybdenum, tantalum, and tungsten, and composite metals such as titanium-platinum.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing a semiconductor device manufactured by a conventional manufacturing method, and FIG. 2 is a sectional view showing a semiconductor device manufactured by an embodiment of the present invention. 1... Silicon substrate, 2... First layer aluminum electrode, 3... Plasma nitride film for interlayer insulation,
4... Opening for interlayer connection, 5... Aluminum electrode of second layer, 6... Polyimide layer for surface protection, 7... Opening for external connection, 8... Aluminum electrode of first layer 9... Hill lock on the surface of the first layer of aluminum electrode, 10... Polyimide layer for interlayer insulation.

Claims (1)

[Claims] 1. A step of forming lower layer wiring on the semiconductor substrate,
a step of covering the lower layer wiring with an organic resin film, a step of forming an opening in the organic resin film to expose a part of the lower layer wiring, and then a step of covering the surface of the organic resin film and the lower layer wiring exposed by the opening. a step of lightly etching and removing the surface of the part using SF ₆ and O ₂ gas plasma, and then forming an upper layer wiring on the organic resin film to be connected to the part of the lower wiring through the opening. 1. A method of manufacturing a semiconductor device, the method comprising: forming a semiconductor device.